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Re: ChipGeek post# 35696

Thursday, 12/07/2006 6:16:37 PM

Thursday, December 07, 2006 6:16:37 PM

Post# of 151748
Chipgeek, you bring up two very interesting points.

First, that AMD's process cycles are quicker than I assumed, which I have already recognized is probably the case.

And second, that Charlie's "A-2" stepping may in fact have been a "B-0", and that he mislabeled it.

And of course, there's still a third item that I haven't mentioned. I assumed an almost unheard of level of validation time, in that AMD would be able to validate and debug their parts all within a month of silicon.

I think this is pretty unrealistic, but I figure it was giving them and their current validation methodologies the maximum benefit of the doubt. But a more realistic interpretation might have assumed 3 months or more per stepping.

I think if you adjust my estimates forward to compensate for faster fab times, and then adjust outward to compensate for more realistic validation times, you'll be roughly left with where I already ended up.

Re: I still think a Q2 launch is a huge long-shot, but it's still possible if the last tapeout was a more healthy B-0.

Agreed, but I still give it a <5% chance of Q2 launch.
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