Advanced Micro Devices Inc (AMD)

[Ixse]

Xeon 2MB / P4EE die size guess
(copy from my post at SI to check if the values are way out of wack or not...)

From Anand: "The 2MB on-die L3 cache takes the Northwood's 55 million transistors and balloons it to an incredible 169 million transistors."

P4 .13 Northwood is between 131 and 146 mm^2 (I found three differrent die sizes for .13 Northwoods 131, 140 and 146 in different discussions and I think the 146 is the most reliable: http://www17.tomshardware.com/cpu/02q2/020610/thoroughbred-07.html). There was someone (Bill Todd at realwordtech I believe to recall; can't find it back) that mentioned cache density of the large cache .13 Itaniums to be ~35mm^2/MB. Itanium large cache is optimized for density so it might in very general terms be comparable with Xeon L3 caches that are optimized for density too. So IF the density would be the same for Xeon/P4EE L3 and IF the 35mm^2/MB is approximately correct then that would amount to a total of between 201 and 216 mm^2 (I think the 216 figure is better than 201 because of above mentioned reason; and pls note that the 2MB L3 is in addition to the 512KB L2 of a normal P4 so the numbers can be added up normally). No idea if the 35mm^2/MB is ballpark though...

So again using the same ifs: IF true the Opteron is only slightly (in the ballpark of 10%) smaller at 193 mm^2 (L3 cache density is much higher than L2 density, ref: http://www17.tomshardware.com/cpu/20030422/opteron-09.html).

Anyone here have an idea if this is remotely correct?

Kind regards,

Ixse