Intel Corp (INTC)

[flumoxed2012]

How can you take this comparison seriously?
This gives NO information on the critical elements of GF's design to size.

[I will sell you the Brooklyn Bridge for $49.95...
I bet you'd buy it....specs are listed in Semiwiki]

BTW, I will bet anyone in here that Intel 10nm is shipping in qty before GF "7nm". And, how about GF 14nm?

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Fins: Intel Fins - The fins are patterned with SAQP and have a 34nm pitch, are 7nm wide and 46nm high. This is Intel's third generation FinFET process. An interesting comment during the talk was that fin height can be optimized by product within an approximately 10nm range. The 46nm height quoted is slightly below the middle of the 10nm range.

GF Fins - The fins are patterned with SAQP and have a 30nm pitch. This is listed as GF's third generation FinFET process, GF's 14nm process was their first generation FinFETs, I am not sure what the second generation was, perhaps an enhanced 14nm version.

[[ SO WHAT ARE THE WIDTH AND HEIGHT OF GF FINS???]]

Gates:

Intel Gate - Contacted gate pitch (or Contacted Poly Pitch, CPP as I call it) is 54nm, presumably created with SADP. Dummy gates at cell boundaries are eliminated allowing neighboring cells to be isolated by a single gate width reducing area by 20%. Minimum gate length is 18nm.

GF Gate - Contacted gate pitch (or Contacted Poly Pitch, CPP as I call it) is 56nm, presumably created with SADP.

[[ SO WHAT IS THE GF GATE LENGTH??? The 20% redux due to dummy excoriation is very clever]]


Strains:

Intel Strain - 7th generation strain with in-situ doped raised source/drains and a novel NMOS strain orthogonal to the drain. The novel NMOS strain increases drive current by an additional 5%

Gf Strain: - raised source/drains. [[[WTF ???}

[[YOU MUST HAVE THE ORTHOGONALS OR THIS THING WON'T WORK.
GF DODGES THIS ONE]]