For those interested in the nitty gritty of the case PTSC needs to get past their 336 oscillator, according to the appeals court being “an oscillator located entirely on the same semiconductor substrate as the central processing unit that does not require a command input to change the clock frequency and whose frequency is not fixed by any external crystal.”
PTSC feels they can get past the first bolded part that was modified by the appeals court because they said in their appeals brief the wording would be ok with them. The problem is if they can get past the second part that was not changed. I suspect PTSC wanted it changed because it is complicated for a jury to understand which makes sense. Is it a game ender? I do not know. All the accused infringing products in the case use a PLL or phased locked loop. Below is what a phased locked loop is defined to be. It is a feedback mechanism. The point is the crystal itself they use is not running at the actual frequency of the on chip oscillator because it cannot generate that high a frequency and does it not DIRECTLY command it with that same frequency. Does "fixed" in the CC mean the actual frequency or does it also include a computer calculated derivative of the frequency of the crystal which is what the PLL uses to control the frequency but not COMMAND it. Can there be an external crystal and that would be ok with the claims construction but just not one that is running at the exact same frequency of the on chip oscillator. Complicated stuff for sure and the answer will determine the outcome. I wish I could tell!
From Wikipedia:
"Phase-locked loops with frequency dividers[edit]
A phase-locked loop (PLL) uses a reference frequency to generate a multiple of that frequency. A voltage controlled oscillator (VCO) is initially tuned roughly to the range of the desired frequency multiple. The signal from the VCO is divided down using frequency dividers by the multiplication factor. The divided signal and the reference frequency are fed into a phase comparator. The output of the phase comparator is a voltage that is proportional to the phase difference. After passing through a low pass filter and being converted to the proper voltage range, this voltage is fed to the VCO to adjust the frequency. This adjustment increases the frequency as the phase of the VCO's signal lags that of the reference signal and decreases the frequency as the lag decreases (or lead increases). The VCO will stabilize at the desired frequency multiple. This type of PLL is a type of frequency synthesizer.
Phase locked loop (PLL)
Using a varactor-controlled or voltage-controlled oscillator (VCO) (described above in varactor under analog VFO techniques) and a phase detector, a control-loop can be set up so that the VCO's output is frequency-locked to a crystal-controlled reference oscillator. The phase detector's comparison is made between the outputs of the two oscillators after frequency division by different divisors. Then by altering the frequency-division divisor(s) under computer control, a variety of actual (undivided) VCO output frequencies can be generated. The PLL technique dominates most radio VFO designs today.
Stability[edit]
Stability is the measure of how far a VFO's output frequency drifts with time and temperature.[5] To mitigate this problem, VFOs are generally "phase locked" to a stable reference oscillator. PLLs use negative feedback to correct for the frequency drift of the VFO allowing for both wide tuning range and good frequency stability.[6]
Repeatability[edit]
Ideally, for the same control input to the VFO, the oscillator should generate exactly the same frequency. A change in the calibration of the VFO can change receiver tuning calibration; periodic re-alignment of a receiver may be needed. VFO's used as part of a phase-locked loop frequency synthesizer have less stringent requirements since the system is as stable as the crystal-controlled reference frequency.
AI
