Saturday, September 10, 2016 5:59:59 AM
That's too black and white. Yes, a big part of power optimization (can) come from post synthesis optimization. Still, there are many things that can and have to be done on architectural/RTL level in order to optimize for power. One basic example would be clock gating, which can be inserted by the synthesis tool but this almost never is as effective as inserting architectural clock-gates on RTL level in addition. Humans are still much more clever than those tools. Also some design choices, as to what steps to take in order to optimize the processor performance and sacrifice power on the other hand are very important. So, everything matters to power, from RTL-design to synthesis and layout. The big problem with this is the feedback loop or iterations, where you need information from layout to improve RTL or/and synthesis. I just went through all this recently and it neither is easy nor straightforward - but possible. The Intel engineers should know how (especially since they know better about their own processes characteristics than any fabless company out there).
Regarding the A/B/C teams: I don't know how Intel is structured internally, but I doubt it is done that way. First of all, there is no clear differentiation between skilled and less skilled professionals, since usually they are experts in some field. This is not a universalist technology anymore, way too complex. So, in order to make a product good, you have to bring in the right people with the necessary skills together and connect them as tight as possible. You don't just need the uber-bright unversalists (well, you need some of them for architecture and such) but instead the right guy at the right time. Intel has them all. It is just a matter of management, not A/B/C teams.
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