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Thursday, June 30, 2016 10:25:57 AM
3DXP in a system that is wired up like DRAM.
You need the chipset and OS to make sure that the only write access
to 3DXP, even if it is on DIMM wired up like a DRAM DIMM, is through
a driver that understands wear leveling etc. Applications which do get
write access have to update it as rarely as possible with write usage
spread out evenly over time. A 100m write cycle cell lifetime sounds
like a lot but it isn't. Reads on the other hand are fine, let them fly just
like DRAM.
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