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Re: flumoxed2012 post# 144213

Saturday, 02/20/2016 12:25:07 PM

Saturday, February 20, 2016 12:25:07 PM

Post# of 151689

I think that we have to accept the fact that the shrinks are going to become harder and have longer cycles, and the effectiveness of doing them is going to become less and less, while the cost becomes more and more. This is in part a competency challenge to management, but I believe in larger part it is the physics wall of approaching atomic scales.



I would 100% back you on this argument if the foundries were seeing similar difficulties. As an investor I really only care about Intel's competitive positioning.

My issue with Intel in process, and the reason that I think this is an Intel execution issue and not a "fundamental laws of physics" problem, is that they appear to be lengthening the interval between process nodes while the foundries kick out new processes at much faster clips.

Now, you could argue that the foundries take smaller steps in between each node. For example, at the 20nm/16nm at TSMC, TSMC got the big area shrink in moving to 20nm, but saved the transistor performance goodness (transition to the FinFET transistor architecture) for the 16nm node while not really shrinking.

This allowed for customers to build fundamentally better products by virtue of the much improved performance/power characteristics of the new transistors.

At the 10nm/7nm nodes, the AMAT exec quote I provided earlier suggests that this will be something of a pattern going forward: do the big area shrink at 10nm, then introduce a transistor performance leap at 7nm.

What I find hard to reconcile with these remarks, though, is the following from a TSMC exec:

TSMC has made a working SRAM at 7nm, Sun reported. The node should deliver 40-45% less area and either 10-15% higher speeds or 25-30% lower power than the 10nm node, he said.



http://www.eetimes.com/document.asp?doc_id=1327725&page_number=2

So it looks to me that TSMC is planning two big node migrations in a row with performance/density improving substantially with each transition.

If this is right, then I have to wonder: why is TSMC able to do two major transitions so quickly while Intel struggles/delays?

Helping investors understand the competitive landscape better is something that BK needs to do. Simply telling us "oh we believe we have a lead" when there are lots of red flags that Intel may be falling behind is just not acceptable.

I'd like to fly out to attend the Intel shareholder meeting in May and ask management to further elaborate on why it believes it has leadership given the plans put out there by the foundries.
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