Advanced Micro Devices Inc (AMD)

[sgolds]

Haddock, perhaps I missed the point you were making in your links. Please state it clearly - why do you think that Intel's queue design in the P4 was for any reason other than an impressive and misleading clock rate? Now, if you are arguing that the original, full-featured design of the P4 was for a higher IPC device, I do not dispute that. My claim was (and is) that when Intel cut features from the P4, they made sure they were left with a large queue design that they had to know would perform poorly with respect to the (otherwise impressive) clock rate.

I am drawing a distinction between the original goals of the design team and the pruning of features as dicated by marketing needs. Where is this not correct?