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Re: fastpathguru post# 143744

Tuesday, 01/26/2016 9:26:33 AM

Tuesday, January 26, 2016 9:26:33 AM

Post# of 151685
So you think that the original poster was being absolutely literal when making his point?

Did you even read the original poster's comment?

"Apple had intended to go with Samsung entirely for the A9 but because Samsung's yields weren't where they needed to be, they did a quick port of the A9 design to TSMC 16FF+."

Such that you feel the need to point out that taking a design from one process to another takes a non-trivial amount of time and effort?

Clearly the original poster has absolutely no idea what is really involved in
even something as "simple" as porting an existing design to a new process.

By the time Apple is producing enough production quality Samsung A9s to
gauge yields the decision to make a TSMC version it is already several years
behind.

To anyone who has the first clue about the IC industry knows Apple would
have had to have two implementation efforts operating in parallel for a long
time to have both Samsung and TSMC based versions of the A9 exist in
the same product cycle at the same time.

If you produce a Samsung A9 and decide Samsung yields suck then you are
basically f***ed for this product cycle. You don't start a TSMC A9 then, you
decide to make A11 or A12 at TSMC. You either fix the yield issues with
the Samsung A9, down spec the part, or you skip A9 altogether and hope for
better luck with A10.

Me, I interpreted it simply as taking an existing design and moving it to a different process, which is easier than designing a processor from scratch.

Clearly you have very little knowledge about IC design methodologies and
the industry in general given your fit about Elmer's reply to the original
post.

I don't talk about my own work publicly but here's a little relevant story
I got first hand from an Alpha designer at DEC back in the day. When EV6
was ported from 0.35 um to 0.25 um (i.e. the EV67) there was a serious
transistor sizing error in a critical path in the FPU that knocked down
top bin clock rates by about 20%. It was an "easy" fix (once they found
the speed path and tracked it down) but it would have required a respin
and restarting the verification process at the silicon and system levels.
The EV6 ports to 0.18 um (one to a Al process, one to a Cu process) called
EV68 were already underway and well along. DEC didn't respin the EV67 to
fix the bug. The fixed EV67 would have ended up reaching market after the
first EV68s. As a result DEC Alpha systems didn't reach the top frequency
target originally envisioned during that year long EV67 market window.

That is the reality of complex ICs like MPUs and SoCs. There is no such
a thing as a simple fix or a simple port.

Not being an expert is not a bad thing. Being an ignorant tw*t actively
being condescending to people who do this for a living is. Even worse is
someone who does understand this and is intellectual dishonest for the
purpose of trolling.
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