Advanced Micro Devices Inc (AMD)

[ChrisC_R]

AMD's 65 nm Trade-offs, per Inq:

http://www.theinquirer.net/?article=32322

........AMD is walking a tightrope. Not only do they have to push their dual core products in the face of Conroe, but they had to find different ways to market the product to consumers. Instead of throwing a lot more transistors at the problem and increasing IPC, all the while transitioning to DDR-2 as well as including Virtualization, AMD focused on power consumption and keeping the die sizes within “reasonable” parameters.

So what can we expect from the first 65 nm parts off the line? Probably something that few folks actually expect. Let me delve into one of the more overlooked properties of transistor design (well, at least to laymen like me). Basically the more stages in a pipeline means that the propagation delay in a signal is cut down and overall clockspeed can be increased, but more stages means that more transistors are being used. AMD is working with several partners to make sure that its 65 nm process is world class. This process encompasses embedded SiGe with dual stress liner and stress memorization technology on silicon on insulator- or e-SiGe with DSL and SMT on SOI for those so inclined. AMD and IBM have stated publicly that this technology allows for a 40% faster switching transistor than from a standard 65 nm design without all the three letter acronyms (TLA’s). In a complex design like a CPU this could mean a theoretical 50% overall clockspeed increase going from AMD’s 90 nm process to AMD/IBM’s 65 nm process all the while staying within the same power envelope.

So, for AMD’s first 65nm design, it had several choices. The first and most conservative choice would be to keep the Rev. F design essentially intact and port it to 65nm and explore the upper boundaries of clockspeed while taking a page from Intel’s Pentium 4 book.

The second choice would be similar to what NVIDIA did with the 90nm G7x series and reduce the transistor count and die size, while improving the clockspeed by a smaller amount.

The final choice would be to transition those extra transistors in those redundant stages into more useful units, and increase IPC all the while keeping clockspeed in the same general area that current 90 nm processors enjoy, all the while shrinking the die size to more manageable levels. This final choice appears to be what AMD has in mind.

This bright fellow, here, as noted earlier, has made a careful inspection of die photos and has come to the conclusion that while Rev. G will be quite similar to the current Rev. F processors, AMD will include an extra complex decoder as well as an out of order load/store buffer and out of order read/write buffer.

This design decision is not exactly a conservative move from AMD, as many were expecting just a shrink of the existing Rev. F. core. Now, these extra units in Rev. G will improve IPC on the K8, but most likely will not allow the design to overtake Conroe and its ilk in overall performance. It will certainly allow AMD to get into spitting distance, and the extra transistor switching speeds that AMD’s 65nm process promises will make for a much more compelling product than the current Rev. F/AM2 processors. Everything else looks the same though, which means the same 3 INT, 3 AGU, and most importantly the same 3 FPU/SSE units which can deliver 2 x 64 bit results per clock cycle peak. It will feature a higher IPC and be able to clock higher than the current Rev. F’s, but Intel still looks to have a pretty hefty architectural advantage with its Core 2 products.

So, while AMD had its hands tied with the 90nm Rev. F processors, it looks to be stretching its wings with its first 65nm product that is due out in December.

It will take Intel a while to fully ramp the Conroe family of products, and until then AMD will still be selling 90 nm processors at a steady rate. Once 65 nm comes, then it will have a more compelling answer to Core 2. In late Spring of 2007 we will see the first dual core K8L processors introduced, and then we will have a whole nother ballgame. µ