Intel Corp (INTC)

[wbmw]

!!! AMD retires large cache Athlons !!!

http://techreport.com/onearticle.x/10175

Looks like Intel succeeded in forcing AMD to ramp their dual core parts faster than they liked in order to constrain their capacity. In order to maintain volumes, they are cancelling all large cache products (both single core and dual core). This should actually help to increase the performance gap between Conroe and Athlon X2 in some applications.

Note that single core parts are now 106mm^2 (up considerably from 84mm^2 for E-step small cache parts, but only down slightly from 113mm^2 for E-step large cache parts) and dual core is now 183mm^2 (up considerably from 147mm^2 for E-step small cache parts, but only down slightly from 199mm^2 for E-step large cache parts). AMD may gain 0-3% performance from DDR2 in some apps, but they will lose a lot more performance by going with smaller caches, while die size overall increases. Maybe F-step was a "step" backwards for AMD?

Here is some text from the article:

The Athlon 64 X2 chips that will be retired are models 4800+, 4400+, and 4000+ for Socket AM2 and model 4400+ and 4800+ for Socket 939 (AMD will continue to supply the Socket 939 4800+ to select OEMs). All of these CPUs have 1MB of L2 cache for each execution core, and obviously the focus for AMD's product lineup will be shifting toward chips with 512KB of L2 cache per core. The only remaining Socket AM2 processors with 1MB of L2 cache would then be the Athlon 64 FX-62 and any Opteron 100-series processors AMD might release for AM2.

Among single-core chips, the Socket 939 versions of the Athlon 64 with ratings of 4000+, 3700+, 3200+, and 3000+ will get the Kervorkian treatment. Also getting the axe will be the Socket 754-bound Semprons 3300+, 3100+, 2600+, and 2500+. These particular single-core CPU models didn't make the transition from the older sockets to AM2, so their fate is not surprising.

By the way, don't get confused with the Sempron model number scheme. AMD "cheated" by upping the model number by 100+ due to the transition to sAM2. So a 2.0GHz 3300+ with 128KB of cache became a 3400+, etc). Therefore, they are only removing the redundancy.