Intel Corp (INTC)

[chipguy]

Does anyone have a link to the tech specs of G5, including its pipeline length?

Poke around the IBM Micro web site. I think you can find a PDF of the uPF presentation
on the 970 from last October.

By the way, the P4 pipeline is indeed 20 stages, but that's only counting from the
instruction trace cache to retirement

That's the branch mispredict pipeline. That is the most critical one in any modern
processor the one usually referred to when discussing the length of its basic
execution pipeline.

The reason why it is much slower than ~3 GHz is that unlike the full custom P4, IBM's
POWER4 family, including the 970, were designed using an ASIC like, highly synthesis
based design flow.

You sure about this? Even AMD doesn't do this.

Yes. This is described in ISSCC 2001 paper 15.2. Over half the non-SRAM macros
in the POWER4 were synthesized. In an Alpha processor, like the similarly complex
EV6, that fraction is exactly zero. The POWER4 likely took a lot less effort and
time to design and debug than EV6. OTOH it needs twice as long a pipeline and
SOI processing to get roughly same clock rate as EV6 at the same feature size.
The SOI processing raises costs, lowers yields, and the longer pipeline drops
performance, especially on integer code.