Advanced Micro Devices Inc (AMD)

[chipguy]

So, while Intel reports the latency for accessing the first sector of a line of cache as 7 cycles, the entire
cacheline takes two accesses, and each is the result of an L1 "miss". Add it all up, and you get the
aggregate 18 cycles of latency that Cachemem reports.

The P4 L1 dcache has a 64 byte line size, the size of an L2 sector. An L1 miss is satisfied and
CPU execution proceeds when the critical sector is fetched from the L2. Measuring L2 latency
with two L1 misses makes no sense because there are two separate and independent accesses
made to the L2 to satisfy them.


Since this "true" aggregate latency is also
applicable to 256K cache, that explains why there is no noticable difference between Willy and
Northwood cache performance.

In access latency measured in cycles. In absolute time latency it is substantially faster. It is also
twice as large which reduces miss rate by an average of 30%, a significant factor for the "cache
performance" of desktop processor with 64B/128B cache lines.

BTW, didn't you previously claim the Northwood's L2 latency in cycles was twice that of Willamette
and that was due to its larger capacity? Do you believe doubling the size of an SRAM or DRAM
doubles its access time?