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Unkwn

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Unkwn

Re: chipguy post# 140618

Tuesday, 04/28/2015 2:36:54 AM

Tuesday, April 28, 2015 2:36:54 AM

Post# of 151686

You are correct. Synthesis takes RTL or a similar behavioral
specification and produces a gate level netlist.


Sure, but I doubt this was meant in the report. They must have referred to a synthesized netlist for power simulation. Everything else would be really inaccurate, to say the least.
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