Intel Corp (INTC)

[Unkwn]

I don't believe it's correct to refer to a post synthesis netlist as RTL.

Mh, honestly I don't know, but it would be really inaccurate to use pre synthesis power simulation. It can be done, but there's a lot of guessing by the simulation tool involved. Post synthesis is far more accurate but still, the layout is missing, with all its buffers and driving load, which can add significantly, depending on the design. I don't believe ARM executed a trial layout and even if they did, it wouldn't mean much for actual designs.

But well, I guess the numbers will stay in that ballpark for the cores - the full SoC is a different animal of course (what ARM compared its simulation figures with).