Intel Corp (INTC)

[Ixse]

Wbmw, Hans wrote about starting at 100nm going to 90nm.

The 15% perf/watt increase I quoted indirectly from AMD (42% increase over no strain, while DSL strain is 24% of that 42% and new SiGe based strain takes care of the rest i.e. 18% additional or ~15% improvement over current DSL).

Hans wrote extensively about Prescott and Yamhill. See: http://www.chip-architect.com So after K8 and Prescott he didn't write as much on his site anymore, but you hardly can't accuse him of being a focussed on AMD exclusively.

re: Another example is the die size estimate of his, which claims a 65nm quad core at 150mm^2. Intuitive estimates would put it at >200mm^2, given that it's twice as many cores and cache as K8, along with a sizable number of improvements, and only one process shrink to make up the difference. So I think Hans' methodology (in which he scales two die photos) uses a lot of assumptions which may not end up proving true.

I trust his estimates over anyone elses here. He's proven himself extensively in this area. You may want to consider the recently released die photo of a 65nm K8 with much denser L2 cache (a newly designed denser type of L2 cache) than expected with a normal shrink. The denser cache is an important reason why the 65nm die is quite a bit smaller than normally expected with a straight shrink. Intel has that kind of denser cache for years already so it's about time too.

Anyways, before saying Hans isn't reliable check his rather flawless record.

Regards,

Rink