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Sunday, May 14, 2006 12:00:16 PM
as a honking big L3 for a high end server chip. That silicon
won't be shared for mainstream use. Is AMD ready to take
on Intel and IBM in low volume, high end server chips? Or
maybe AMD will do this with funding from Sun for a SPARC
replacement for Sun's mid to high end systems.
As far as ZRAM's small cell capacitance, that is simply a
circuit design issue. You keep the number of cells on each
bitline low, say 64 to 128 instead of 256 to 512 in a conven-
tional DRAM, to keep the read out signal manageable. And
you up the refresh rate to as high as necessary - the refresh
rate needed will depend strongly on maximum device junction
temperature.
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