Advanced Micro Devices Inc (AMD)

[chipguy]

If it delivers as advertised, ZRAM, could potentially reduce AMD’s die size by up to 40% and reduce AMD’s cost per chip by up to 50%.

That is so utterly clueless as to be amazing. If ZRAM works as
advertized it would mean that AMD could integrate massive
L3 caches using up to 50% or so less area than an SRAM
based L3 of the same capacity. For the weenie little caches
AMD uses today the area savings benefit of ZRAM is marginal
if it exists at all because the cell efficiency vs capacity scaling
properties of DRAM type memory strongly favours very large
memories because of all the auxillary circuitry required and
area expansion of pitch matched circuitry around cell arrays
due to the extreme aspect ratios required.

It looks like these idiots simply took the cell size ratio vs SRAM
claimed for ZRAM and scaled down the die area consumed
by the L2 current K8 devices.