Re: Yeah, I know cache has redundancy so higher yield per sqmm, but they will be big chips to cache up for the bus bottleneck, and a breakneck schedule does have high screwup risk.......
Actually, Intel's quad core chips are likely to be easiler to manufacture than AMD's single monolithic design. The Core base die size is about 145mm^2, and Intel's quad core designs will use two of them. And as far as yield, manufacturing two 145mm^2 parts is a lot easier than manufacturing a single 290mm^2 part. Note that AMD's quad core design will be more like the latter, even at 65nm.
As for schedule, yeah I'd agree that rushing things leads to screwups, but that's assuming that the Core intro dates have been rushed. It's just as possible that the validation cycle went better than expected, thus allowing them to reduce the need for a stepping, and bring it to market sooner. It will be interesting to see if Intel can make their schedule targets and still ramp at the rate they've been projecting. If they do, it will certainly be to their benefit this year.
