Intel Corp (INTC)

[mas]

By following I mean the incorporation of similar instructions in other ISAs and subsequent implementations. On slide 19 of the Sparc pdf I linked they give the order of improvement over T5 in query decompression as 10. Now T5 had a weak core so probably 3-4 over their last M6 gen core. Generally 32-core 20nm M7 has a chip performance improvement over their 12-core 28nm M6 of 2.9-3.5 (slide 12) for 2.67 more cores. The individual cores are 8-threaded and look in the Silvermont class on first viewing and so the M7 should roughly have more or less a similar throughput performance as the top-bins of Power 8 or Xeon although about half in single-thread.

http://www.setphaserstostun.org/hc26/HC26-12-day2-epub/HC26.12-8-Big-Iron-Servers-epub/HC26.12.820-Next_Gen_SPARC_Phillips-Oracle-FinalPub.pdf