Intel Corp (INTC)

[mas]

Good info on CMOS scaling and especially liked the detail in one of the links in that article which is worth printing ...

http://semiengineering.com/will-7nm-and-5nm-really-happen/

The options

In the near term, the leading-edge chip roadmap looks clear. Chips based on today’s finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture.

One of the leading contenders for 7nm has been the high-mobility finFET, which is a finFET with III-V materials in the channels. The III-V finFET would supposedly consist of Ge for PFET and indium-gallium-arsenide (InGaAs) for NFET.

“Germanium is making good progress,” said An Steegen, senior vice president of process technology at Imec. “III-V is tricky. It still needs more work.”

In fact, III-V technology is challenging and could get pushed out to 5nm. “Ge and III-V channels are still hot contenders at 7nm,” added Aaron Thean, director of the logic program at Imec. “However, the narrow bandgap of these materials are presenting problems for low-leakage transistors. The outlook for these (III-V) materials is moving from 7nm to likely 5nm. This does not preclude the use of these materials in the source/drain in the nearer term.”

So with the possible delay of the III-V finFET, what’s next for 7nm? Imec is weighing several transistor options, namely gate-all-around, quantum well finFETs, and SOI finFETs. Considered the ultimate CMOS device in terms of electrostatics, gate-all-around is a device in which a gate is placed on all four sides of the channel. “At a certain point in your process (for gate-all-around), you are going to undercut that fin. Then you come in with a dielectric in the gate and you basically fill in underneath the channel, which is now a nanowire,” Imec’s Steegan said.

“There is, of course, SOI,” she said. “You can also have an effective quantum well. (In this structure), you build in an effective energy area to basically shut down the leakage path.”

For the channel materials at 7nm, Imec has narrowed down the options to two choices—an 80% composition of Ge for PFET; or a 25% to 50% mix of Ge for PFET and 0 to 25% of Ge for NFET with strain relaxed buffers. “The perfect candidate, of course, is germanium,” she said. “The silicon devices are operating at 0.8 and 0.75 volts. But the germanium devices are operating at 0.5 volts. So you have exactly what you want in performance as well as the electrostatic behavior. But, of course, you have lower Vdd, so you save power.”

Following 7nm, the industry is looking at several transistor options for 5nm—gate-all-around; quantum well; SOI finFETs; III-V finFETs; and vertical nanowires. “We are looking at all of the aspects for vertical nanowires,” she said. “We are exploring how we grow the channels. And do we use channel last or first integration schemes?”