Advanced Micro Devices Inc (AMD)

[chipguy]

So, for a Vcc_max of 1.417V at an Icc_max of 70A, the
maximum power is 99.19W. Now, I recognize that this is
not likely to be seen except for the worst of circumstances,
but if we are to speak of maximum power, this is the figure that should
appropriately be used.

That is the maximum instaneous power consumption but there is nothing
that says that this can be sustained over a period comparable to the thermal
time constant of the die or package.

The current consumed by microprocessors varies from clock cycle to clock
cycle depending on what is going on inside at that instant. Icc_max likely
occurs when a P4 issues 6 uops in a single cycle while performing a
write transaction on the FSB and internal L1 to L2 transfer or vice versa.
I think you will agree that a P4 can not sustain the issue of 6 uops per
cycle for very long. Even disregarding misses, the trace cache can only
fetch 3 uops per cycle and the uop buffer between the trace cache and
scheduler will quickly empty.

For the purposes of thermal design it is likely that the maximum power
that can physically be dissipated by a P4 is a fraction of your 99 W figure.