Friday, March 10, 2006 4:11:23 AM
LOL, if that's conservative, what's "realistic"? Frequency^2? 
When they talk about performance deltas, I'm assuming they DON'T mean performance of applications, but rather, the chip frequency.
Duh.
BTW, here's another reference, since you seem to have blocked out the SiGe announcement:
Andy Wei, a member of the technical staff based at AMD Dresden, described a new process that AMD will first retrofit into its 90-nm microprocessors, and then use in its 65-nm designs going into production in the second half of next year at AMD’s new 300-mm fab in Dresden.
IBM will use the new process for its initial 65-nm processors, said Gary Bronner, an IBM project leader at the IBM-AMD alliance based in East Fishkill, N.Y.
“Strain engineering has replaced gate oxide scaling as the means to improve PERFORMANCE, because of leakage considerations at the gate,” Wei told a crowd of several hundred at a Tuesday IEDM session.
AMD and IBM last year used a dual-stress-liner approach for their 90-nm transistors, putting differently configured nitride capping layers on top of the NMOS and PMOS transistors. At the 65-nm node, the partners added an embedded SIGE layer similar to what Intel used at the 90-nm node. Wei said “a big boost came when we added the embedded SIGE” at the source and drain regions of the PMOS transistor.
The PMOS devices now run almost as fast as the NMOS transistors. Wei said the new process will allow design engineers to better balance the size of the N- and PMOS transistors to achieve PERFORMANCE improvements at the product level that he said could approach 50 percent.
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=174901200
When they talk about performance deltas, I'm assuming they DON'T mean performance of applications, but rather, the chip frequency.
Duh.
BTW, here's another reference, since you seem to have blocked out the SiGe announcement:
Andy Wei, a member of the technical staff based at AMD Dresden, described a new process that AMD will first retrofit into its 90-nm microprocessors, and then use in its 65-nm designs going into production in the second half of next year at AMD’s new 300-mm fab in Dresden.
IBM will use the new process for its initial 65-nm processors, said Gary Bronner, an IBM project leader at the IBM-AMD alliance based in East Fishkill, N.Y.
“Strain engineering has replaced gate oxide scaling as the means to improve PERFORMANCE, because of leakage considerations at the gate,” Wei told a crowd of several hundred at a Tuesday IEDM session.
AMD and IBM last year used a dual-stress-liner approach for their 90-nm transistors, putting differently configured nitride capping layers on top of the NMOS and PMOS transistors. At the 65-nm node, the partners added an embedded SIGE layer similar to what Intel used at the 90-nm node. Wei said “a big boost came when we added the embedded SIGE” at the source and drain regions of the PMOS transistor.
The PMOS devices now run almost as fast as the NMOS transistors. Wei said the new process will allow design engineers to better balance the size of the N- and PMOS transistors to achieve PERFORMANCE improvements at the product level that he said could approach 50 percent.
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=174901200
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