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Three cores in the A8X ?
Isn't UMC still in the game?
SMIC as well but will either still be around in the foundry FinFET era ?
IBM have a 22nm PD-SOI process which as non-Intel processes is not bad albeit quite expensive I suspect at 15 metal layers. As G-F have not got a 20nm process yet this automatically becomes the smallest process G-F offer now. I don't suspect any mobile takers for it but other high asp devices ... maybe. I think this deal makes sense for both parties as G-F pool more of the IBM process family manufacturing base with IBM evolving future processes for them as a result.
I suppose ever since PowerPC died, in a volume sense, with the loss of the Apple contract this was the inevitable conclusion. This consolidates G-F though as one of the top 3 foundries along with TSMC and Samsung and IBM can now concentrate exclusively on process research. Intel indirectly caused this as well as the creation of G-F in the first place via its competition against both IBM and AMD in the mpu marketplace.
System P users waiting for Power 8 refresh ?
Denver is a 64-bit ARM chip and the SHA subtests indicate it is being tested in that way.
Core-M single-thread performance/clock for the subtests where Denver = 1
Integer
BZip2 Compress = 1.68
Lua = 1.56
JPEG Decompress = 1.54
BZip2 Decompress = 1.43
AES = 1.40
Dijkstra = 1.26
JPEG Compress = 1.17
PNG Decompress = 1.17
PNG Compress = 1.06
Twofish = 0.97
Sobel = 0.95
SHA2 = 0.69
SHA1 = 0.33
Floating Point
DGEMM = 8.06
SGEMM = 5.14
BlackScholes = 4.12
N-Body = 3.72
Ray Trace = 2.44
Mandelbrot = 2.10
Sharpen Filter = 1.49
Blur Filter = 1.39
SFFT = 1.12
DFFT = 1.05
I disagree with you that Intel did/does not have competitors in the Server space, it had all the Riscs above and AMD below for decades now. The ARMy will have to outperform Intel in any market they want to take from it and their combined chips are just not up to it either in PCs or Servers.
Intel has in fact seen them off at the tablet pass which most posters here kind of predicted against what was considered common Analyst 'wisdom' only a couple of years ago. Those fancy graphs of Warren East where ARM just blithely marched in and took PC/Server marketshare away from Intel easy as pie were just pure wild fantasies with no basis in any factual reality like we said at the time.
There is a red 'Report TOS Violation' button on the bottom right of the page. This goes straight to the site admins.
As if punching up with a boutique variant of a cash-cow product line with effectively no competitors, is anything at all like being hell-bent on entering a market as a non-incumbent with a products that can undermine the cash cow...
AMD already tried that.
ASO's profits were always limited by how many rocket missions Boeing and Lockheed Martin could garner and as they made the two most expensive medium-range rockets in the world, Delta IV and Atlas V, this was a situation that was not going to improve any time soon especially with cheaper entrants like SpaceX's Falcon 9 entering the fray who prefer to process their own missions. So ASTC as a space satellite processing company had known limits outside of its control that limited revenue to about $20m a year.
Now the spectrometer business has far more profit potential, for example if Battelle win the Army's next generation chemical detector award with 1stDetect technology this will initially be a $50-100m revenue contract and that is just one particular application.
The possibilities in so many markets are endless going forward if you believe 1stDetect's tandem MS/MS miniature mass spectrometer is ground-breaking and leading the market and I do as most competitors use heavier quadrupole-ion technology for their miniature mass spectrometers against which Rigaku have already validated 1stDetect's tandem MS/MS accuracy with, which is why they chose the lighter 1stDetect technology as there was no degradation in accuracy.
p.s. the Director Remuneration Committee decide Pickens's salary, bonus and benefits and not himself.
His father has had no involvement/influence with Astrotech .. ever. He also built Code Corporation into a success about 15 years ago and it is still going strong after he left so he did not fail there.
p.s. how's that imaginary big IMSC TSA order coming along ? Still MIA ?
$750K, approved by 82% of voting shareholders
http://ih.advfn.com/p.php?pid=nmona&article=63323986
and how exactly is this micro-controller company related to Intel ? The market is too silly for words sometimes !
In theory, RISC should have been running circles around CISC. In practice, we see the opposite.
RISC was one solution to silicon implementation characteristics around that time and is not necessarily superior by design unless we are talking about the performance/power of 1mW processors. Remember that more RISC instructions are needed to perform the same task as CISC instructions so there is one disadvantage there not only in more work on the execution side but also because the more powerful the instruction the smarter ways you can think of to implement it when you have to break it down into simpler machine instructions.
Also the 8 register format of x86-32 is not that much of an impediment if you see how often it performs better than x86-64 due to smaller pointer size and x86-64 has 16 registers which is all ARM has at any one time in 32-bit mode. 32 over 16 probably buys you 5% at most in integer. AMD once did a slide showing 16/32 register gains over the 8 of x86-32 and the low hanging fruit was definitely between 8 and 16.
The constant high-performance of x86 now for over 20 years in its desktop market shows that rather than CISC being a disadvantage it is probably an advantage in this market as both Intel and AMD have beaten in performance/power the best that Power, Sparc, PA-Risc, Alpha, MIPS and ARM have thrown at them over that time.
The fundamental advantage I believe is that CISC x86 allows you to get more performance for a given issue width due to the more powerful instructions and higher issue width correlates with greater power usage which is why the 200W of Power 8 is tolerated in servers but is a no-no in desktops. The decoder/register disadvantage is just noise in this respect. I know CISC x86 has evolved from humble beginnings rather than being designed as a master ISA but it really is quite good when the rubber has hit the road and the evolved x86 ISA plays some part in this I believe.
They will be back when the sale cash shows up next quarter in earnings .
All the SpaceX Dragon missions are processed by SpaceX themselves. Yes Pickens does get paid a lot for a company with currently very very little revenue . To be fair to him though he bought 10% of the company off a selling institution, SMH, so he did the other shareholders a favor by removing those selling shares and he did need that 20% vote to push that ASO sale through.
Also the other 10% that was given to him was a reward for getting rid of $50m+ Spacehab debt at around $5 a share which was a pretty good deal by him in hindsight considering the price has never been that high since and it kept share count around 20m.
p.s. it cost $500K to buy out Texas's 1stDetect options so 1stDetect could be brought back into ASTC.
Astrotech was not involved with either SpaceX or Boeing in their Space Taxi capsules, Dragon and CST-100 respectively, so there is no future role to miss out on.
However it is true to say that the original Spacehab division failed in that regard in not securing a follow-on spacecraft award but it was tough when the competitors were so rich and offered expensive inducements like new rockets (SpaceX/Orbital) or considerable legacy experience and capital funding (Boeing).
For a long while this little company successfully strode with Space Giants but that original part of it was assimilated in the end by one of those giants.
Looks like ARM have brought A57 integer performance/clock (at least as measured by Geekbench3) up to about 2/3 of the very latest Core which is not bad at all. Of course Core ultimately will clock twice as high meaning the performance difference between the high ends is about 3 to 1. On floating point A57 looks about half the performance/clock.
Also they got all 8 cores working in that big.little chip as multi-core scaling seems consistently just better than 4 which shows the 4 little cores are contributing to achieve this. So what does this all mean then competition wise going forward. Probably Intel will have to use higher bins than otherwise it would have wanted/expected to maintain the expected performance differential between Core and the 64-bit ARMy.
Wow, you make it sound like markets never change ... ever ! Back to mainframes and dumb terminals I guess then .
p.s. Core-M will become the new market 0) ultra-premium in that simple little table of yours.
Samsung is going to use its own foundry using ARM chips purely to provide a volume base for its foundry and not fall into the IBM low volume loss making trap. Of course Intel will prefer to sell x86 chips but that may not be possible with Apple it it wants its business and Intel will need to have something in any Apple contract that makes the foundry price device dependent, like Qualcomm does with its licensing, as Apple may want to use Intel foundry to move its A chips up the price ladder and Intel needs to be compensated for that if x86 chips are replaced.
You misunderstood me, I mean Apple using Intel as a foundry like TSMC. The point about Intel's 10nm is that it could offer a one year cadence from the foundries FinFet processes to Apple and will be more than twice as small as 14/16FF which are still using a 20nm back-end layout in reality. This could be an easy $10+ profit per chip for Intel.
For mad Nenni that was almost a sane post . I have never bought the idea that Apple would dual-source its A chips. It is too much trouble to try and fit different processes just for one year's iteration. You would expect TSMC to get A9 as 16FF is an incremental step from their 20nm. Coincidentally I think Intel has a good chance of getting the successor A10 with its 10nm as that will be coming a year later than 16FF while the foundries twiddle their thumbs in 2016 just rolling out 14/16FF. Intel's 10nm will allow Apple to jump to quad-core and still improve single-thread performance over 16F.
Broxton (or whatever it's called now) is not cancelled which is a foolish thing to say as it is the next-gen Android performance successor to Merrifield but then again he could not be relied upon to make a completely sane post.
Alex Cho ? LOL. He wrote some of the most stupid uninformed unintelligent Intel bashing articles when it was the 20s ! I am surprised after that debacle he has 1 follower let alone 1403 !!
Pretty sure the Chinese govt will make sure the Chinese chip makers end up with the lion's share of that low-end tablet market going forward.
It just so happens Rockchip will have an Atom x86 chip for them if that is the case .
I am talking about future potential with 14/16FF.
Cyclone is reasonably pipelined with a branch mispredict penalty of 16 cycles (14-19 typical). I suspect it is power considerations that is holding it back from 2+ GHz clockspeeds as they increased the ipc on an already wide fat cpu going from A7 to A8 which probably took up most of the power benefit shrinking to 20nm although the next iPad will probably gain another 100-200 MHz due to the tablet form factor. It will need the power reducing feature of FinFETs though to get a lot closer to 2 GHz. Cyclone is basically an ARM Alpha clone which is why it gets close to Core in ipc and is not indicative of usual ARM mobile cpus which are a third/half as wide as Cyclone. Nvidia's Project Denver is as wide but it is in-order which reduces that advantage.
http://www.anandtech.com/show/7910/apples-cyclone-microarchitecture-detailed
Regardless though the merchant ARMy have nothing like the potential Cyclone has as they are already maxed out (or close to) on clockspeed so Core-M's ascendancy over these is safe.
Well then it does not exactly show the latest greatest A15 in a good light either
(K1-64) Performance is meh
Not really a surprise for an in-order Transmeta-like chip that requires a good compiler and predictable application to really work well. Itanium had this problem too but that had a lot of execution units, short pipeline and very low cache latencies to make it a respectable performer generally outside of its favored applications. Project Denver is not so blessed but regardless it should at least win on the battery endurance side as compensation but that appears to have fallen short too. What good is a dual-core ARM chip that is not appreciably faster or longer lasting than its quad-core cousins ?! Ah well, Nvidia's problem !
Intel Opens Door on 7nm, Foundry
EUV not needed at 10, 7nm
http://www.eetimes.com/document.asp?doc_id=1323865&print=yes
“My day job is working on [research for a process to make] 7 nm [chips and] I believe there is a way without EUV,” said Intel fellow Mark Bohr, responding to a question after a talk on Intel’s new 14 nm process.
The optimism is significant given the core lithography used for patterning chips hasn’t had an upgrade in more than a decade. Chipmakers generally don’t expect the much-delayed extreme ultraviolet (EUV) lithography in time for 10 nm chips, but many still hold out hopes it could be ready for a 7 nm generation.
“I am very interested in EUV [because it] could really help scaling and perhaps process simplification, reducing three or four masks to one in some cases,” Bohr said. “Unfortunately, it’s not ready yet -- the throughput and reliability are not there.”
Bohr did not give any hints about how Intel will make 7 or even 10 nm chips without EUV. However he did note at 14 nm Intel is using triple patterning on one or more critical layers.
Although wafer costs rose at an accelerating rate for the last two nodes due to the need for more masks, Intel continues to pack more transistors in a given area of silicon. The density offsets wafer costs, leading to the cost-per-transistor decline, Bohr said in his talk on Intel’s 14 nm process.
“One of the fundamental benefits of Moore’s Law is smaller feature sizes, primarily to get lower cost per transistor so we can do more things” in a similarly sized chip, he said.
Intel already announced it has started making in volume chips using a 14 nm process at a lower cost per transistor than its prior 22 nm generation. It also said it is in development of a 10 nm process that it believes will deliver lower cost per transistor ...
1stDetect Awarded New Contract for Next Generation Chemical Detection Solution
http://ih.advfn.com/p.php?pid=nmona&article=63556995
Company collaborates with Battelle to improve current military chemical detection solutions
1st Detect, a subsidiary of Astrotech (Nasdaq:ASTC), announced today its breakthrough technology has reached a key milestone in the military’s test and evaluation process for Multi-Sample Identifier Detector (MSID) solutions, by being awarded one of the competitive prototype contracts for the Next Generation Chemical Detector (NGCD) program.
“1st Detect is well positioned to be rapidly matured into a tactical sensor solution for defense and security applications along with our strategic teammate, Battelle, the prime contractor,” said Thomas B. Pickens III, Chairman and CEO of Astrotech. Battelle brings 25 years of chemical and biological defense expertise. “We believe this collaboration, in alignment with government direction, will contribute to an accelerated development timeline for NGCD because the efficacy of product design iterations can be immediately vetted with actual chemical warfare agents,” he said.
“We are very excited about the award,” Pickens said. “1st Detect’s disruptive technology will allow us to provide our military with the proper technology needed to save lives.”
1st Detect Corporation has developed an instrument that revolutionizes the chemical detection and analysis market by delivering lab performance mass spectrometry in a small, affordable and easily portable package. The 1st Detect mass spectrometer is capable of detecting a wide variety of chemicals including residues and vapors from explosives, chemical warfare agents, toxic chemicals, food and beverage contaminants, and pollutants. These abilities make it an ideal tool for a variety of applications in the research, security, industrial, process flow and healthcare markets.
Transition Services Agreement with LMT
http://www.sec.gov/Archives/edgar/data/1001907/000157104914004194/nny1401636_8k.htm
http://www.sec.gov/Archives/edgar/data/1001907/000157104914004194/nny1401636_ex10-1.htm
http://www.sec.gov/Archives/edgar/data/1001907/000157104914004194/nny1401636_ex10-2.htm
On August 22, 2014, Astrotech Corporation, a Washington corporation (the “Company”), in connection with the closing of the transactions contemplated by the Asset Purchase Agreement (as defined and described below), entered into a Transition Services Agreement (the “TSA”) with Lockheed Martin Corporation, a Maryland corporation (“Lockheed Martin”) and Lockheed Martin’s wholly-owned subsidiary Elroy Acquisition Company, LLC, a Delaware limited liability company (“Buyer” and, together with Lockheed Martin, the “Buyer Companies”), pursuant to which the Company and Buyer agreed to provide the other party with certain services, including, among others, services related to benefits, human resources and payroll administration, cash management, financial statements and compliance, each of a type currently provided by or for the Company or the ASO Business (as defined below), as applicable, after the consummation of the Asset Sale (as defined below).
The Company has agreed to provide services to Buyer for a period of up to one year and Buyer has agreed to provide services to the Company for a period of up to six months. Each party has the option to extend the term of the services provided by the other party for a period of one year. Services provided pursuant to the TSA may be terminated by the party receiving such services on an individual basis upon 30 days’ notice to the providing party. The party receiving services shall pay the providing party, as consideration for such services, on a time and materials basis, fees based upon a set fringe rate and fee rate and the salary of the employee of the providing party who is providing such services.
A8 looks like a higher clocked Cyclone on the cpu side which is kind of what I thought it would be and I expect that to be the same again at 16FF. They have used 20nm primarily to increase endurance on a relatively wide fast dual-core which also had slack in its pipeline length just to increase clockspeed a bit too with a better lower power process which is the sensible way to approach non-marketing based mobility.
Talking of long-lasting dual-cores vs marketing based skus looks like Merrifield maybe finally breaking cover apparently ranged against a Mediatek Octa (quad-A17, quad-A7) in the same 5-inch Lenovo Vibe X2. Performance/endurance comparisons should be very interesting and apparently Merrifield is being positioned as the more powerful version which should educate the masses a bit.
http://www.dailytech.com/article.aspx?newsid=36475&ref=y
http://www.engadget.com/2014/09/09/apple-iphone-event-2014/
New payment system for iPhone6 and AppleWatch.
hence..it might be very difficult for them to show any growth at all next year
Unlikely with Broadwell, Cherry Trail, Broxton and Windows 9 all tipping up.
http://nvidianews.nvidia.com/News/NVIDIA-Files-Complaints-Against-Samsung-and-Qualcomm-for-Infringing-Its-GPU-Patents-bb4.aspx
http://blogs.nvidia.com/blog/2014/09/04/nvidia-launches-patent-suits/
http://www.anandtech.com/show/8492/nvidia-files-patent-infringement-complaints-against-qualcomm-samsung
We are asking the ITC to block shipments of Samsung Galaxy mobile phones and tablets containing Qualcomm’s Adreno, ARM’s Mali or Imagination’s PowerVR graphics architectures.
With Samsung, NVIDIA’s licensing team negotiated directly with Samsung on a patent portfolio license. We had several meetings where we demonstrated how our patents apply to all of their mobile devices and to all the graphics architectures they use.
We made no progress. Samsung repeatedly said that this was mostly their suppliers’ problem.
Without licensing NVIDIA’s patented GPU technology, Samsung and Qualcomm have chosen to deploy our IP without proper compensation to us. This is inconsistent with our strategy to earn an appropriate return on our investment.
We are now seeking the courts’ judgment to confirm the validity, infringement and value of our patents so that we can reach agreement with Samsung and its graphics suppliers.
"We just made no progress and they've not put a real offer on the table," Nvidia co-founder and CEO Jen-Hsun Huang said in a conference call with analysts Thursday. "When you've been using technology for free for a long time, I guess it's hard to sign up for a large and significant license agreement."
http://blogs.barrons.com/techtraderdaily/2014/08/12/intel-bulls-cheer-watershed-mailed-fist-in-14-nano-too-late-asks-raymond-james/
Ahh, Mosesmann (and Covello), perpetually bearish and also perpetually wrong on INTC. How much money have they lost for anybody foolish enough to actually believe their nonsense over the years ? Mosesmann once put a $40 target on NVDA in 2011 when it reached $26 so that turned out well too for all the bagholders since then .
Foreign cash vs US cash ?
http://www.chiploco.com/haswell-ep-e5-2600-v3-specs-35055/
Cores, clockspeeds and prices for all tastes
Model Cores CPU Frequency TDP Price
E5-2603 v3 6 1.60 GHz 85 W €169.95
E5-2609 v3 6 1.90 GHz 85 W €239.95
E5-2620 v3 6 2.40 GHz 85 W €319.95
E5-2643 v3 6 3.40 GHz 145 W €1149.00
E5-2630 v3 8 2.40 GHz 90 W €509.00
E5-2640 v3 8 2.60 GHz 90 W €699.00
E5-2667 v3 8 3.20 GHz 145 W €1519.00
E5-2650 v3 10 2.30 GHz 105 W €869.00
E5-2660 v3 10 2.60 GHz 105 W €1069.00
E5-2687W v3 10 3.10 GHz 160 W €1579.00
E5-2650L v3 12 1.80 GHz 65 W €989.00
E5-2670 v3 12 2.30 GHz 120 W €1179.00
E5-2680 v3 12 2.50 GHz 120 W €1289.00
E5-2690 v3 12 2.60 GHz 135 W €1549.00
E5-2683 v3 14 2.00 GHz 120 W €1369.00
E5-2695 v3 14 2.30 GHz 120 W €1789.00
E5-2697 v3 14 2.60 GHz 145 W €1989.00
E5-2698 v3 16 2.30 GHz 135 W €2379.00
E5-2699 v3 18 2.30 GHz 145 W €3029.00
Windows "Threshold" Tech Preview Coming Soon
http://www.tomshardware.com/news/microsoft-windows-update-technology-preview,27467.html