Here's another
http://www.investorshub.com/boards/read_msg.asp?message_id=1179136

Haddock, I still don't buy the x86-64 story.

But you would if it was Intel?

"Given the proper foresight, I think it would have been better had Intel forced a 64-bit x86 architecture, instead."
- You in http://www.investorshub.com/boards/read_msg.asp?message_id=1108937

What you say is the same thing I've heard a dozen times before from other AMD enthusiast

I think it's important to keep two arguments separate:

1: It's easy to port to x86-64 because it is so like x86. I agree that this is mainly a red herring. The exception may be compiler-writers, ie Portland in the current case.

2: It's easy to move to 64 bits with Hammer because you can move your apps one at a time rather than all at once. This is a stronger argument to me.

The argument in the article to which you responded was #2, but you put up the #1 straw man and then attacked that. (And of course it's not entirely a straw man, since it is admittedly regularly wheeled out by the AMD faction).

if you have a reference then please post.

http://www.investorshub.com/boards/read_msg.asp?message_id=1178351
http://www.investorshub.com/boards/read_msg.asp?message_id=1176024
http://www.investorshub.com/boards/read_msg.asp?message_id=1176816
http://www.investorshub.com/boards/read_msg.asp?message_id=1177474

The references have been posted here in the thread already.

Linux will run on every PowerPC control processor to route packets.

Really? You're not getting it confused with the Newisys motherboards? I would be surprised if the PowerPC control processors in Red Storm were running any OS at all, never mind something as heavyweight as Linux.

On compute nodes they run some very exotic Unix clone, used to be called Unicos many years ago.

They are running the Light Weight Kernel LWK, also called catamount. See http://www.investorshub.com/boards/read_msg.asp?message_id=1176816 page 16. The preceeding pages explain why they are not running a Unix-like OS on the processing nodes (because if the OS takes a timeout from running the compute task that tends to delay the surrounding CPUs too as they wait for data to do the next step in the simulation).

The information on how the machine is built is available, why are people speculating when they could just read the PDF?

It is a question of the basic building block - 1P or 4P. My point was to indicate that Linux is already set up to distribute threads over a 4P system, so if they send a set of threads to a Linux running on a 4P

They aren't even running Linux on the compute nodes!

TSMC posted surprising earnings, I heard. So demand is up.

"In the second half of May, customers placed orders as they were afraid they could not get enough product due to SARS," Ying said, adding that those orders showed up in last month's figures.
http://www.taipeitimes.com/News/biz/archives/2003/07/08/2003058560

I think it's a little early to call the end of the downturn to be honest. Would be lovely if it was already over.

http://www.businessweek.com/bw50/content/mar2003/a3826049.htm

This guy travels a lot in techland and reports what he observes:
http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=19003785
http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=18933337
http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=18950211
http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=19075628

find it surprising that Power4 and Itanium 2 both receive lousy scores on this benchmark

Here's more info on CTH and Alegra. It's not obvious to me either why I2 doesn't do better on them.

http://sherpa.sandia.gov/9231home/papers-frame.html

We'll see. I don't think even AMD has made up their minds how exactly they will name and position their CPUs.

I don't think AMD will have a serious advantage here, especially with the slower Athlon 64s with half or one quarter of the cache and single channel memory controller.

That's not for competing with P4-HT-3.2-800MHz, it's for competing with Celeron. Since Celeron has very poor price-performance (and performance) that may well be possible.

>> Sandia will be able to run 64- and 32-bit applications
>> on the AMD Opteron processors right away," he says.
>> "That means they can run 99 percent of their existing
>> code with just a recompile, and converting 32-bit
>> applications to 64-bit mode won't require a heroic effort."
>
> I'd like to see them actually do it, rather than just
> repeating PR. I'll be impressed once the headline reads,
> "Sandia labs was able to port all of their HPC software
> to 64-bit in a matter of weeks.

I don't think that's what they are planning to do, read it again. They are planning to run their 32 bit code in 32 bit mod 'with just a recompile'. Presumably the recompile is to move to Linux and/or take advantage of new optimisations, since the Opteron can run all the instructions the PII-based ASCI Red could run.

Then they can convert to 64 bit at their leisure for the apps that need/benefit from it. That's not going to kill them, esp. not if it's written in Fortran where pointer size is hardly visible to the programmer.

This is the real benefit of Opteron: You can port your software (or persuade your ISVs to port) as and when you need to do it, rather than having to go through every single piece of performance-relevant code on the system and make sure it's there for 64 bits.

Take a look at Cadence's website for example. They have dozens of apps. A given user/workstation will need several of them. Not all of them need 64 bits, but they are mostly performance critical. The ones that need 64 bits are being ported to x86-64 now. The rest run on the same workstation with competitive performance, no need to reboot, no need to run on a remote server, no need for two workstations under your desk.

The large, high I/O count system fabric ASIC made
by IBM Micro is likely many times more expensive than the Opteron it connects to.

Presumably by IO count you mean pin count?

Why do you think this chip will be so expensive?

Seems buzz-word compliant: serial ATA, USB-2.0, 5.1 channel surround, RAID, AGPx8, Ethernet. They misspelled Opteron, but they do anticipate their chipset being used with Opteron too, it seems.

Edit: So when do we see chipsets with integrated graphics?

Duron to be brought back as AthlonFX.

At least that's my interpretation of the Rojak Pot article: http://www.theinquirer.net/?article=10385

I wish they would plot the overclocked systems in a different colour. Who is going to overclock an Opteron workstation?! While they are at it, they should do Athlon XP and P4 in different colours too!

Conclusion: Gotta get to 2GHz (or 2.4!).

All the info I can find on Red Storm says 2GHz Opterons with 1Mbyte L2 cache.

after all, who cares about the other positions if you don't have #1?

Not sure that Red Storm will be #1 in the world, actually:

Based on existing supercomputer projects and their expected arrival, company officials from SuSE and Cray believe that upon its completion Red Storm will be the fastest supercomputer in the United States. http://www.infoworld.com/article/03/06/23/HNsusecray_1.html?platforms

the idea is that AMD probably offered a large enough discount on the CPUs to get the design win the first place.

Well, they are probably stock Opteron 246s (1 HT link for the ASIC, 1 HT link for the local SCSI etc.) so by the time the machine is actually built they will likely be $2-300 parts max and Cray can buy them on Pricewatch. That puts the cost of CPUs at about $2.5million, ie not all that significant in the context of a $90m project. I don't think a discount was required, Opteron just naturally isn't all that expensive.

I guess if AMD had delivered special 4-HT-link Opterons then that would have been a different story with a different price tag. Probably they couldn't agree on a price, and AMD gets almost the same level of prestige with the current solution.

As far as I can see, AMD isn't contributing anything else to the project apart from the Opterons. Of course the machine could be later upgraded to faster Opterons like ASCI Red was upgraded from PPros to PIIs.

Because AMD is willing to fit the bill so that they can get the #1 ranking on the top-500 list

This is a Cray project as far as I can work out. Are they not just using AMD CPUs?

The worst
case message passing delay is half of that or 68 us.


Why do you keep saying this, when it has been pointed out that the correct number is 5us? Clearly messages that merely pass through a node are somehow patched through faster than those destined for the node.

Here's a side-by-side comparison of ASCI Red and Red Storm.
http://www.shudo.net/diary/data/20021118/ASCI-Red-Storm/

ASCI Red had 1-hop and max latencies of 15us and 20us, so Red Storm is a big improvement. There aren't a lot of machines in the 10000-processor class to compare with, but apparently it's difficult to get really good latency figures. I think these figures are for a complete MPI message, rather than a single word of data being passed from one chip to another. I'm having trouble finding the equivalent figure for Altix, but this http://groups.google.com/groups?selm=3E32D511.3520114A%40sgi.com suggests it is in the 0.5us range (for 32 CPUs), so only about 4-10 times faster than Red Storm, which has 30 times more CPUs.

Having said that, the figures for the SGI machine are very good, and I expect them to do well with the system. So well, that I bought shares - not too many though, since they have obvious financial problems, and I'm not well equiped to judge how long they can survive (with shareholder capital intact).

Last week I posted a simple calculation here showing that when you subtract the number of pins required for two HT channels from 940 then you get a number less than 754, implying that there are enough pins for dual DDR already in the smaller socket.

I think perhaps that calculation was too simple.

It's not just the number of pins involved, but their definition. Even if there are enough pins for dual DDR on Socket 754 it seems they are not defined for that use (certainly I never heard it if they are). Suddenly changing the definition of pins on Socket 754 would be much worse than moving to Socket 940 for the premium version of A64.

Anyway there may be extra ground an power supply pins needed for the dual-DDR version. Or there may be routing issues that mean you can't use arbitrary pins.

theInquirer has gotton inaccurate to the point where it is more misleading than enlightening.

I'm sure you can find things they got wrong, but your argument would work better with just one example that has actually been proved wrong, rather than one you don't like the sound of.

With DRAM you must go with what is mainstream, otherwise you are doomed.

What's your personal opinion about SOI - was it a mistake? Several people expressed opinions, mostly negative.

You didn't ask me, but I think it's pretty clear now that it was a mistake to do a 130nm SOI process as anything other than a research project. Two different 130nm projects stretched their resources and betting the farm on SOI was a big risk.

The Barton reversal happened pretty fast. If they did not reverse Opteron that means things are not that bad.

Reversing Barton just meant they could base Barton on the already existing bulk Athlon design. There is no bulk Hammer design as far as we know. It is that bad IMHO.

I don't think anyone linked to this article (AMD fails to launch x46 Opteron in June)
http://www.theinquirer.net/?article=10254
but I was on the beach for a week so perhaps I missed it.

2. AMD learned more about Prescotts capabilities and concludes 128-bit memory channel is indeed needed for launch already to prevent from any QS-rants after Prescott-launch - unless anything above 2 GHz is achievable.

This is most likely the reason - they have decided to launch A64 with dual memory channels, ie with the same socket as Opteron 14x. Socket 939 could be an attempt to bring back the lost market segmentation between A64 and Opteron motherboards.

Disappointing that they make this decision so late if true.

Opteron Launched on April 22nd, "With Strong Support From Server, Software Vendors"

Actually I think the 2nd tier server vendors did offer reasonable support, the problem is that the motherboards were not available. Judging by the number of announcements there was strong chipset and motherboard support on the way for Athlon64, unfortunately AMD launched the Opteron instead and wrongfooted all their 'supporters'. I guess AMD thought those guys would just build Opteron boards and chipsets instead but they just aren't the sorts of companies that do server equipment, and anyway these things take time. Combine that with Solectron not making an Opteron motherboard and you have the resulting sad situation of Opterons being available, the motherboards not being as easily available.

This seems to fit in with a general pattern of AMD not taking care to coordinate the various parts of their virtual gorilla. Moving from 200->266->333->400MHz FSB was far too many tranitions, and AMD would have been better off cutting 1 or 2 of them out (moving early to a faster speed, giving the dual-channel chipsets a performance advantage and the single channel chipsets a cost advantage.)

Unexpected FSB changes, last-minute launch schedule changes etc. mean the virtual gorilla is looking a little punch-drunk right now.

I'm hoping the situation will improve 'automatically' for now, in that the Athlon64 launch date has been fixed well ahead and no changes are to be expected in Athlon or Hammer infrastructure requirements for the foreseeable future.

Well, you learn something new every day!

The RISC chips that came soon after the 386 were [...] too [...] power hungry

Huh?

http://groups.google.com/groups?selm=37FD6996.2B368AF%40igs.net

With half the cache and lower clock frequency than Barton

In the scenario from the article the clock frequency wouldn't be lower. If the frequency is lower then they can't do that trick (reduce cache size, boost frequency, keep the name).

Ever stop to think that Intel might end up successful with Itanium in the long run?

Obviously that would be bad for AMD. I think it's a way off if it happens, though. Right now I don't see any evidence that Intel are aiming I2 at any high volume markets.

No one is going to pull the plug until that data is available. To think otherwise is a 'Droid fantasy.

Pulling the plug on Itanium is and AMD fan's nightmare, not fantasy. That would mean Intel competing with AMD in the x86-64 space.

No doubt when the endorsement of Opteron by "core kernel hackers" turns out to be worth less than a cup of warm spit

I think you'll find I haven't expressed an opinion on the value of that endorsement until now. Given the warm and open exchange-of-ideas atmosphere you aren't spreading on the subject I think I'll continue not to do so.

you and your ilk

The Concise OED says of 'ilk' "Usually derogatory and therefore best avoided".

The Webster's article is lie (intrans., in the sense of rest) vs. lay (trans., in the sense of place). Ie "I lie on the couch = I rest on the couch" vs. "I lay my baby in the bed = I place my baby in the bed". It has nothing to do with lie in the sense of telling untruths.

Websters seems to argue both sides!

Not at all. They tell you the prescriptive grammar rule, and the descriptive grammar rule and discuss whether the prescriptive rule will ever be changed to fall into line with the descriptive rule.

But if it does rise to respectability, it is sure to do so slowly: many people have invested effort in learning to keep lie and lay distinct.

Even if intransitive lay rises to respectability that will not make the older intransitive lie wrong. You corrected accepted (correct) usage to the controversial (wrong) usage.

In grade school, I was taught that 'lie' should be used for 'untruths' and 'lay' should be used for 'position' or 'proximity'.

I think you should sue your grade school. They taught you something that "others will judge you unfavorably" for (to quote Websters).

The 'correct' prescriptive grammar rule is that:

Lie (past tense lay) is for proximity or position
Lay (past tense laid) is something you do to something/someone/yourself
Lie (past tense lied) is to tell an untruth

Perhaps you think my comment about how many machines "core kernel hackers" buy was flippant

Yup.

More on Thorton and different cache sizes of Athlon64

http://rss.com.com/2100-1006_3-1021832.html?type=pt&part=rss&tag=feed&subj=news&foo=...

It looks like AMD hasn't made up their minds on the correct strategy. I wonder why they feel the name "Duron" doesn't work for them.

My thinking is that they would do better to have different names for different chips to avoid confusion. I think there might be legal complications in changing the specs of existing names after the fact. Eg. if bin splits improve and they feel they can save money by replacing an 1800MHz 1Mbyte A64 3100+ with a 2200MHz 256kbyte chip then perhaps they should call it 3050+ or 3150+. There are plenty of spare names: 3001+ perhaps?

How about the first two digits indicate the relative performance on a set of benchmarks (like QS does now), the next is the speed, the last is the cache:

0 1400MHz
1 1600MHz
2 1800MHz
3 2000MHz
4 2200MHz
...
9 3200MHz

0 256kbytes
1 386kbytes
2 512kbytes
3 768kbytes
4 1Mbyte
5 1.5Mbyte
6 2Mbyte
7 3Mbyte
8 4Mbyte
9 6Mbyte

So the first chip above would be a 3124+ and the second would be a 3140+

Nah, too complicated. Better to revive the Duron name and give it inflated model numbers to match Celeron's MHz.

I see Intel is moving towards including the cache size in the name of the CPU. Starting with the chips that run at "2600A MHz", but now with the "Itanium II 6M" and "Itanium II 3M".

>> If it's the core kernel hackers you are talking about,
>> they love Opteron and Athlon64 and they don't really give
>> a monkey's who has the big money.
>
> Great news for AMD!!!
>
>
> How many machines a year do "core kernel hackers" buy?

Chipguy, I was merely trying to explain what UpNDown meant when he said:

Now you know why the Linux leaders are so enamoured of it.

and you apparently didn't know what he meant by Linux leaders, started talking about "corporate IT types".

But I'm glad to see my attempt to narrow down the language gave you a new chance to wheel out your "Linus' opionion doesn't matter" line. Nice to know I brought a little simple pleasure into your life. After all, we are just here to score points off one another, aren't we?

I should also point out that money does not lie, but it may lay

On the contrary, lay is transitive, so unless someone is getting laid by money, the word is lie.

http://www.kathyide.com/quiz.html

From that page:

Lay means "to set down" or "to put or place someone or something in a horizontal position." It is a transitive verb requiring a direct object that receives the action of the verb.

Lie means "to rest or recline" or "to be in a prostrate position." It is intransitive, and takes no object.

"AMD Opteron Processors Win Best of Show at ClusterWorld"

the lack of 64-bit flat addressing is not a huge barrier for entry in this market.

http://biz.yahoo.com/bw/030627/275163_1.html

And Linux people know

"Linux people" are a very diverse group indeed. If it's the core kernel hackers you are talking about, they love Opteron and Athlon64 and they don't really give a monkey's who has the big money.

http://groups.google.com/groups?q=itanic+group%3Alinux.kernel

At some level of low cash -- $500 million perhaps

So this stuff is secret, or should we be poring over Edgar documents?

Another possibility is that at about $500 million cash, AMD will have trouble making payments for its operating expenses and debt payments.

Maybe I'm being hopelessly naïve here, but can't they use the $500m for that?

The condition for bankruptcy of a company is an inability to pay debts as they come due.

It seems to me that's about 3 quarters off, assuming things don't get better. Or worse!

I remember www.downside.com used to have a page detailing when .com's were due to go bust by dividing burn rate by cash. Seemed to work OK. If AMD is like the .com's then they won't go bust until their cash is gone.

I wonder if AMD could somehow get a statement of principle from the Linux leaders about AMD64 support?

They already have a press-released statement from Alan Cox, and there was an Inq story of Torvalds dissing Itanium and talking up x86-64.

Perhaps as a quid pro quo for the excellent support that AMD has offered, and no doubt will continue to offer, to Linux development?

Nothing compared with what Intel paid for IA64 support (Trillian project).