Well, I thought they'd be interested, though the gang of amdzone kids will no doubt object strenuously.

Also, the cores are ~10% bigger.

I accounted for that part. ;) It's just interesting that you can start with either the 1155 SB part, or the Westmere EP part, make the adjustments based on core & cache differences, and basically get to the same 360-370 mm^2 estimate. Gives added confidence in it.

That "certain someone" (cough Hans Cough) doesn't realize, apparently, that the desktop parts will be based on the SB *EP* / *EN* Jaketown parts, not an EX part. And how he would reason, oh it must be 2/3rds the size of Nehalem-EX... just bizarre. I think he wants to believe it will be 460 mm^2.

I guess he's in for a rude awakening. If only he looked at his own diagram and reasoned it out:

http://www.chip-architect.com/news/Llano_vs_SandyBridge_vs_Westmere_s.jpg

And then there's the fact that Llano comes in at 225mm^2...so much space used for uncore / GPU and there's not even L3 cache!

GlobalFlounderings says 22nm product intros in 2013. So much for, "closing the gap."

http://www.globalfoundries.com/newsroom/2010/20100901_Roadmap.aspx


With risk production set to begin in 2H 2012, GLOBALFOUNDRIES is well on its way to delivering 22/20nm technology to customers for product introduction in 2013. The 20nm technology offerings will come in two varieties: a High Performance (HP) technology designed for wired applications such as servers and media processors, and a 20nm Super Low Power (SLP) technology designed for power-sensitive mobile applications. GLOBALFOUNDRIES also will have access to a 22nm Super High Performance (SHP) technology designed for devices requiring the utmost in performance. The 22/20nm technologies are planned to be a full node shrink from 32/28nm, and will utilize next-generation HKMG technology and strain engineering to enable the area and die cost scaling the industry has come to expect with each technology generation. Test chip shuttles for customers will begin running in Fab 1 in 2H2011.


Well, let's see.

I guess the 32nm product intro gap will probably be 15-18 months, depending on whether Llano products launch in Q2 or Q3 2011.

So, with Intel product launches on 22nm in Q1 2012, that 15-18 months could become anywhere from 12-21 months for 22nm, depending on when in 2013 the GloFo 22nm products launch.

I'm sorry, but I'm having difficulty understanding your usage. Perhaps google translate or a similar tool might be of assistance?

You know, I think AMD charges more for "unlocked" defective parts that let the kids attempt to unlock a turned-off core and see if they can get it to work. It's such a bonus!

Ok, how about, not "defect" recovery, per say, but maybe a core or two is a bit power-hungry...

Here's another way to estimate the 8-core die size:


248 (Westmere 6-core EP die)
+ 2 * 28.5 ( 2 extra westmere cores )
+ 8 * 1.0 ( SB core + L3 slice is 1 mm2 bigger than Westmere core + L3 slice)
+ 8 * 11.1 * .25 (L3 slices are 25% larger)
+ Y (what else can there be? transcoding silicon? more northbirdge stuff?)
-----

335 + Y

Surely they can completely disable a core and then not worry about it at all? I take your point about determining exactly where the fault lies, but modulo that?

crushed is "not in a position to meaningfully affect Intel pricing", which is arguably not the case today in many segments.

However, sticking with a gate-first HKMG process @ 32nm may help get them all the way to "crushed" next year.

Enh, appletv was never a big seller. I believe Jobs calls it "a hobby". On the bright side, the rumor was that AMD had won the biz.

It will probably take Android Gingerbread (coming next month?) or the subsequent "Honeycomb" release next year to drive the non-Apple tablet market. I suppose some "fat" Windows 7 tablets might see success with a suitable UI layered on top.

OTOH, as the appleheads continue to saturate on iPads, it is unclear that the enthusiasm will spread much outside of that group, even for the iPad itself.

I will say, again, that the iPad is however the perfect device for playing "words with friends", an online scrabble game. :)

Apparently, cap-layer debris is a major cause of the delightful yields one sees with a gate-first HKMG process.

ill fated ha ha ha lol

I know! If Sandy Bridge is "ill fated", what must the slipping-towards-2012 stuck-on-a-broken-GloFo-process Bulldozer be?

To quote Intel's Francois,

Q: What is big, power-hungry, and slow?
A: A Bulldozer.

No doubt they could make a 6-core die if that proved to have more volume than could be supplied from 8-core partial defect recovery.

I question why they'd bother with an IGP on a 6-core desktop part, though... seems like that is clearly in the high-end/enthusiast camp, and while, sure, some crunchers don't need much GPU... seems to me that most potential customers in that segment either plan on a discrete card or at least wouldn't care that much about the lack of an iGPU.

The 8 core Sandy Bridge will likely end up larger than 350mm2

I don't think so, or at least, not much.

If you start with the 225 mm^2 4core+IGP, looking at the die, you get to 5 cores by swapping out the IGP. Each (core+2MB L3 slice) is just about 30 mm^2. So 3 more cores gets you to 315 mm^2. Now, the 2011-socket Sandy's have 2.5 MB L3/core instead of 2, and looking again at the 1155 photo, .5MB L3 is about 3 mm2, so you need 8x that, or 24 mm^2.

That's 339 mm^2. I figure the IMC is doubled, some extra interconnect, so add a bit more, but should still be 350-370 or so.

I assume the 6-core parts are just recovery of partially busted 8-core parts.

And Llano is basically the same 225 mm^2 size, based on the wafer they showed.

Apparently, the BD 4-module/8-core part is estimated at ~310 mm^2.

Sandy-2011 8-core/16-thread should be in the same general ballpark, maybe 350 or so.

I was able to patch some of GloFo's bad PR urls:

http://globalfoundries.com/newsroom/2010/20100901_ARM.aspx

http://globalfoundries.com/newsroom/2010/20100901.aspx

http://globalfoundries.com/newsroom/2010/20100901_Roadmap.aspx

http://globalfoundries.com/newsroom/2010/20100901_Freescale.aspx

Apparently, there is something "major" in there... not sure I can find it, though.

Yeah, how could Intel's only competition in the x86 space possibly be relevant to an Intel investment board?????????!!!!!111

I mean, really.

So, clearly not some weird heterogeneous-cored thing. In other places, there is speculation that the top "modules" are the fake ones, the bottom ones blurred but likely correct.

by JF-AMD on Wed Sep 01, 2010 9:36 pm
OK folks. About a week or two ago the request came to us to show the Orochi die at a GF event.

Obviously we were more than OK with our partner doing this, but at the same time, doing that would mean that we would definitely have our die out for the world to see. So, the reason that things are different porportions is that some are photoshopped. I am not saying which is correct and which is not, obviously.

Also, other areas were intentionally blurred in order to prevent the competition from knowing what it going on.

You are seeing a die, but you really can't even be sure that you are looking at the exact dimensions or shape.

Actual die shots are released with launch. That is a single Orochi die.


http://www.amdzone.com/phpbb3/viewtopic.php?f=52&t=137904&start=0

So, at this stage, what does it mean that yields are still troubling? Does fixing that (potentially) mean respinning products, or tweaking the process while using the same mask sets, or both?

LOL, all the press links on their website lead to a server crash page. Nice.

Turns out the answer is more typically AMD: It's not an actual die photo. It's been photoshopped.

http://www.xtremesystems.org/forums/showpost.php?p=4534638&postcount=48

Thanks. So the "N" represents a frequency bin, I take it, possibly 100MHz wide, or something like that? And this is max frequency for the part, or for a type of transistor?

Can anyone explain what AMD is trying to say in slide 17 of that pdf?

32nm HKMG / Fmax distribution ?

They seem to be suggesting that they're doing better than the previously expected median of whatever that is...

max frequency of something or other?

Interpretations appreciated.

Yeah this http://phx.corporate-ir.net/External.File?item=UGFyZW50SUQ9NjExNDN8Q2hpbGRJRD0tMXxUeXBlPTM=&t=1

is much better...

Truly odd.

"fusion" means a GPU on die... I don't see how the CPU cores variations between top and bottom module pairs would have anything to do with a GPU? (which is clearly not present at all, nor should it be, given that BD APUs are not due until some time in 2012)

Looking at the cores, the top ones appear to have extra "stuff" on the L2-side, and lopping that away, they look fairly close to the bottom ones. I wonder if that is the FPU area, and they are toying with cutting the FMA, or 128 vs 256 or something.

Orochi is an internal name-- zambezi is client, valencia server, and interlagos is 2x valencia MCM server.

I think AMD said at hotchips that desktop would follow server, but still squeak into 2011.

Of course, that is all modulo glofo.

Interestingly, even correcting for perspective, the top two cores appear to have subtle differences from the bottom 2. Bizarre. Some experimental sample? I can't believe they would really have 2 types of cores in a final product.

Well, when looking at those parts, things like the memory speed are changing as well, and that has a big impact.

Here, we are speculating that all else equal, this 12 EU (it seems, i.e. "2 cores") unit may be running at either 650 or 850 MHz, but turbo could bring it up to 1300 or 1350 MHz.

So in the case that turbo is not active for the GPU in this sample, I'd expect a nice performance gain in real world performance.

Poor Charlie thinks it's a fusion part. Apparently the iGPU is invisible-- must be some advanced technology GloFo has there. ;)

I'd normally expect this level of error from Fuad.

Even JF-AMD flatly told the amdzone kiddies that No, a single thread cannot run in both halves of a module at once.

The only competitive position AMD will have with BD, IMO, is if Intel does not answer the Interlagos MCM part, where AMD lowers clocks and voltages, and puts 8 modules/16 cores on a part.

In the client space, 8-core SB-2011 will slaughter 4-module/8-core BD.

I saw that. OTOH, given that the "turbo" for the part is a package-spanning controller that can trade off between cpu and gpu, and was noted as definitely disabled for the cpu, I suspect the gpu was also unable to turbo.

In that event, the 12 EU part might have been running the whole time at 650 or 800, instead of turboing up to the 1300 to 1350 max.

So it is still possible there is something on the order of 2x performance in reserve.

EDIT: I see you addressed this very issue in a reply. I do think it would be unlikely they somehow locked down cpu turbo but left gpu turbo active, given the way turbo 2.0 has been described.

While the mobile GPU bases itself at 650 vs 850, it turbos nearly as high. (Turbo freqs: mobile is 1300 for a bunch, 1150 others; desktop is 1350 some, 1100 others)

The turbo probably matters most of the time, as it is presumably unlikely to be stressing all the cpu threads as well as the GPU.


Not sure if doubling EUs really quite doubles performance; probably depends on whether the bottleneck is in the "shaders" or not.

Funny how times change...

I give up. This is all I can find: http://www.airproducts.com/Electronics/semiconductor.htm

I believe Q4 2008 had at least 2 warnings. Of course, this was in rather extreme circumstances, with a shockwave propagating backwards from PC OEMs to component suppliers like Intel, like nonlinear traffic jam behavior.

First warning: http://intc.com/releasedetail.cfm?ReleaseID=347468&ReleasesType=Financial%20News

Second: http://intc.com/releasedetail.cfm?ReleaseID=357860&ReleasesType=Financial%20News

You just know JF-AMD will claim this result is about the differences in memory and drives, and has nothing whatsoever to do with the CPUs...

Interesting slide posted, apparently from Intel early this year.

Notes the future of the desktop:

SB: 2-8 core products
IvyBridge: 2-12 core products (sockets same as SB; 1155 & 2011)
Haswell: 4-16 core products

http://www.xtremesystems.org/forums/showpost.php?p=4530583&postcount=557

I'll see if I can embed the image here (the "redacting" is a joke by the guy who posted it):

On various forums they have JF-AMD fudding the fanboys that Bullduster will destroy Intel in every which way.

It's not clear that JF-AMD has yet figured out that "IPC" means performance/frequency not just performance. He seems to confuse the two concepts frequently.

Yes, that fool thinks boilerplate from the risk section of company filings means that there are problems. Someone pointed out to him that AMD has a similar section, but I don't think it registered.

I mean, the guy was arguing that a stronger GPU than the one in Sandy Bridge will be needed because lots of people like to play Farmville on their Facebook page. Really.

Joel must not have paid attention to the Anand SB preview. That part's GPU featured only 6 execution units, as opposed to the 12 some will use, and it may not have had GPU turbo active (The CPU turbo was disabled).