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WSJ(12/11) Intel Wrestles With Challenge Of Chip Leakage
By Don Clark
SAN FRANCISCO -- Andrew Grove has seen the semiconductor industry overcome many hurdles since the 1960s. But there is a big one ahead that has the chairman of Intel Corp., and its top scientists, scratching their heads.
The issue is leakage, the electrical current that tends to escape from chip circuitry when it isn't being used. As Intel and other companies have gone from squeezing hundreds of thousands of transistors on each chip to hundreds of millions, the current lost by each tiny circuit sharply increases the total power a chip consumes.
More electrical current costs computer users money and increases the heat generated by chips, making it hard to package them into personal computers and other systems. Mr. Grove, in a speech to chip engineers here, showed an unusual frankness in disclosing just how stumped his scientists are.
"What we can't get rid of is power leakage," Mr. Grove said. "Current is becoming a major factor and a limiter on how complex we can build chips."
That is a big concern, because many companies have built businesses around the ever-increasing performance of chips, driven mainly by the shrinkage of transistors. If anything disrupted that pattern of progress -- known as Moore's Law, after Intel co-founder Gordon Moore -- the future of Silicon Valley could change radically.
An ordinary chip might draw 12 watts of power and leak 12% to 15% of it. But leakage accounts for 40% or so of the power consumed by Intel's most advanced chips, Mr. Grove said during his keynote address at the International Electron Devices Meeting. In a few years, when chips have as many as one billion transistors, they may leak 60 to 70 watts of power, he predicted.
Speaking metaphorically, Mr. Grove said that "in our headlong pursuit of performance . . . we are heading toward a nuclear reactor" in terms of electrical current consumed by chips.
Engineers have some time to work on the problem. Mark Bohr, an Intel chip scientist who holds the title of senior fellow, said the company is working on new insulating materials and other techniques to fight leakage.
"We have things in the pipeline that can get us through the decade," Mr. Bohr said following Mr. Grove's talk. "Then it gets really questionable."
(END) Dow Jones Newswires
12-10-02 2156ET
wbmw -
Looks like the flood gates are opening. IBM announced their systems last week, HP demoed their superdome implementation, and now SGI is getting ready for a 64-way system. Things are looking better for Itanium 2.
This is great news.
EP
HP, Unisys tout Intel servers
By Stephen Shankland
Special to ZDNet News
December 10, 2002, 4:14 AM PT
High-end Intel servers took two steps forward Monday as Hewlett-Packard demonstrated an Itanium version of its top-end server and Unisys charted new territory for servers using the Xeon processor.
HP has been the most vocal advocate of Intel's Itanium processor, the foundation of an HP plan to unify its server lines. The computer maker on Monday demonstrated one key promise of its Itanium strategy, a single system simultaneously running three operating systems: Microsoft Windows, Linux and HP-UX. HP-UX is HP's version of Unix.
Although companies such as now-extinct Sequent have tried to build high-end Intel servers, the systems haven't caught on widely with banks, retail stores and other customers with heavyweight computing jobs. That's changing with the arrival of more powerful processors such as Itanium and of less crash-prone versions of Windows--Windows 2000 and its successor, .Net Server 2003, due for release in April 2003.
While Itanium is at the forefront of Intel's challenge to processors such as Sun Microsystems' UltraSparc and IBM's Power, it was Intel's comparatively lowly Xeon chip that helped Unisys achieve the sixth-highest score yet in a much-watched server speed test.
The ranking, posted Monday, is the second-highest an Intel server has achieved in the Transaction Performance Council's TPC-C speed test. In addition, the Unisys system was the least expensive on the list at $2.7 million.
Intel servers have traditionally been lower-end, lower-priced systems that ship in larger quantities than do more powerful Unix servers. Intel servers now are creeping up the ladder, however, with Microsoft warming to the high-end server market and Intel servers sales poised to outpace Unix systems using RISC (reduced instruction set computer) chip rivals such as UltraSparc and Power.
HP, which showed its Itanium high-end system at the Gartner Data Center Conference Monday in Las Vegas, demonstrated its top-end Superdome system with 28 Itanium 2 processors. This system can be "partitioned" into several independent pieces, each with its own operating system. Superdome already ships with HP's own PA-RISC processors, but a version with 64 Itanium 2 processors and supporting 512GB of memory is due in 2003.
In the demonstration, a 20-processor partition ran Windows and Microsoft's SQL Server database software, a four-chip partition ran HP-UX Unix and Oracle's database software, and a four-processor partition ran Linux with desktop software, HP said. Although a single Superdome cabinet can accommodate 32 chips, four processor slots were left unused in the system, said John Miller, director of server marketing for HP's business-critical systems group.
Competing higher-end servers from Sun, Fujitsu and IBM can all be partitioned. However, servers from Sun and Fujitsu can run only Solaris--Sun's version of Unix--while IBM's servers can run IBM's Unix and Linux. Dell Computer is rising in the ranks of server sellers, but doesn't have a server that can be partitioned.
However, Unisys is shunning Unix, pitching its ES7000 line with Windows or a mainframe operating system. NEC, meanwhile, has a 32-processor Itanium 2 system that can be partitioned. The server runs Linux and will be able to use Windows when the next version arrives in April 2003.
SGI, which focuses on the technical computing markets, plans in January to begin selling a 64-processor Itanium 2 sever running Linux that also can be partitioned.
Unisys achieved its sixth-place result with an ES7000 Orion 230 server using 32 2GHz Xeon MP processors running a preliminary version of .Net Server 2003. The system clocked is one notch below an NEC system.
You Suck -
Where are all the digit head longs on days like today??
Maybe they all went to the same place you disappear to when Intel goes up? Myself, I'm perfectly happy to watch Intel go lower because I'm looking to buy low and sell high. We are in a Bear market. Are you just realizing that? Share prices go down. That's why it's a Bear. You seem to gain some perverse pleasure here. Personally I'm happy to see you make money but you could use an attitude adjustment.
EP
Uncle Smickers -
Well, DUH! Why the heck would you want to try that in the first place?
I think the rest of us saw the point. Too bad you didn't.
EP
Haddock -
All that validation stuff is only necessary if they actually want to sell it.
Great line!
EP
wbmw -
Is IBM still planning on using partially depleted SOI?
You know as much as I know.
EP
subzero -
What's up with this? Press Release Source: Intel Corporation
Interesting!! I guess we'll find out tomorrow!
EP
IBM discloses combo strained-silicon/SOI technology
By Mark LaPedus
Semiconductor Business News
(12/04/02 07:30 p.m. EST)
EAST FISHKILL, N.Y.--IBM Corp.'s Microelectronics Division next week is expected to announce a radical and combination strained-silicon/silicon-on-insulator (SOI) technology for use in making high-performance chips at the 65-nm (0.065-micron) node.
IBM has already fabricated an SRAM, based on the “strained-silicon-on-SOI” technology in the lab, but commercial chip products are not due out until the 65-nm node in the 2005 time frame, according to officials from the East Fishkill-based organization.
Initially, the company plans to develop and make high-performance microprocessors, build around the combination strained-silicon/SOI process.
Based on an epitaxial process, IBM's technology combines the inherent advantages of both strained-silicon and SOI. SOI enables higher frequency devices, while strained-silicon offers low parasitic capacitance within a chip structure.
Chips based on the combination process offers 20% more performance, as compared to devices with standalone SOI technology, said Byoung Lee, manager of CMOS process integration at IBM Microelectronics. Lee is the lead author of a paper on the subject, which will be will be presented at the International Electron Devices Meeting (IEDM) in San Francisco from Dec. 9-11.
IBM's announcement follows a similar disclosure by AmberWave Systems Corp. In October, the Salem, N.H.-based company claims to have developed a strained-silicon on SOI process. AmberWave also develops a standalone strained-silicon process, of which it licenses to chip makers (see Oct. 16 story ).
IBM--which claims to be taking a different approach to that of AmberWave--appears to be developing a “silicon-germanium-on-SOI” technology. Using IBM's approach, the first layer of the chip would be silicon foundation, followed by a layer of silicon dioxide, silicon-germanium, and then strained-silicon.
Others are also jumping on the strained-silicon bandwagon as well. Recently, for example, Intel Corp. announced plans to develop a strained-silicon technology at the 90-nm node. Intel is also developing SiGe transistors for that node as well, it was noted.
IBM, which is already offering SOI and SiGe, will not have strained-silicon until the 65-nm node. At that time, IBM's process will consist of the combination strained-silicon/SOI process.
The company still claims it is still ahead of Intel in the process technology race. “Intel is developing strained-silicon on bulk at 90-nm,” Lee said. “We don't see the need to have strained-silicon at 90-nm, because SOI intrinsically has better performance [than strained-silicon at 90-nm],” he said.
The IBM technologist was referring to the company's SOI technology, which is being used with its existing high-end processors at the 130-nm node, and most likely, at 90-nm.
Intel Paves the Way for Hyper-Threading
Dec 03, 2002 (Internet.com via COMTEX) -- In preparation for its next generation of PC and server semiconductors, Intel Tuesday released new compiler software designed for Windows and Linux operating systems.
Software developers use compilers to translate a programming language, such as C++ or Fortran, into the machine language understood by the processor. Version 7.0 of Intel C++ and Intel Fortran compiler software was built specifically for use in the latest Intel Itanium 2, Intel Xeon and Intel Pentium 4 processors-based systems, which boast the company's new Hyper-Threading technology.
The Santa Clara, Calif.-based chip making giant said Hyper-Threading chips allow multithreaded operating systems and applications to view a single physical processor as if it were two logical processors. Intel says it's similar to watching television while talking on the phone. Intel says that can increase performance of a multithreaded application by 40 percent.
Version 7.0 for C++ is now available for download starting at $399 each. Version 7.0 of the Fortran compilers for Windows and Linux are being sold for $499 and $699 respectively. The compilers will be available on CDROMs by the end of the month.
The new compilers support many features of Compaq Visual Fortran, including command line compatibility and include extensive integration into Microsoft Visual Studio. The Linux version provides GNU compatibility to C++ with the adoption of the C++ application binary interface. Intel said its compatibility features make it easier for application developers to start using Intel compilers to see how their applications might perform better on the Intel Architecture.
"Intel compilers enable software developers to make their applications more competitive with improved performance," said Jon Khazam, director of Intel's Software Products Division.
The new version 7.0 Intel Compilers also include an auto-parallelization option that automatically looks for opportunities in applications to create multiple execution threads and enhancements to OpenMP support. OpenMP is an industry standard that enables the use of high-level directives that simplify the creation and management of multi-threaded application software.
"Our application is heavily used in very large and time consuming data mining applications, so it is of great importance to get the best performance possible," said Dr. Fons Rademakers, Senior Scientist at CERN. "We ported 800,000 lines of C++ and 90,000 lines of C source code to the Intel compiler in one afternoon, an activity that previously took us about a week."
The idea for Hyper-Threading was the brainchild of Intel senior engineer Glenn Hinton back in 1993. The company has begun filtering in the multithreading designs into its Pentium 4 processors as early as 1996.
By Michael Singer URL: http://www.internet.com
Copyright 2001 INT Media Group, Inc. All rights reserved. Republication and redistribution of INT Media Group content is Expressly prohibited without the prior written consent of INT Media Group, Inc.. INT Media Group, Inc., shall not be liable for any errors or delays in the Content, or for any actions taken in reliance thereon.
=DJ Asia DRAM Report: DDR-400 Usurps DDR-II As Next Standard
By Dan Nystedt Of DOW JONES NEWSWIRES
TAIPEI (Dow Jones)--Intel Corp. (INTC) is playing kingmaker in the contest to determine which memory chip will dominate the market throughout next year, and the chip giant's backing of an incrementally faster version of existing memory is likely to delay the coronation of next-generation DDR-II chips.
Previously thought to be a mere stopgap until DDR-II enters the market in 2004, DDR-400 is itself now seen as a contender for the title of "industry standard."
Industry sources say DDR-400, double data rate memory chips that run at 400 megahertz, appeared on Intel's product development roadmap early last month. That means Intel will begin designing hardware to allow its popular Pentium 4 microprocessors to work with DDR-400 - something the chip giant hadn't intended to do.
Intel, however, wouldn't confirm nor deny whether DDR-400 is in its product strategy.
According to motherboard and chipset makers in Taiwan, Intel's decision was due to its desire to pair its Pentium 4 with faster memory and concern about the heat problems that afflict faster memory chips, including DDR-II.
Since Intel processors power around 80% of all personal computers on the market, an Intel stamp of approval means instant recognition from the rest of the computer industry.
Companies already adept at producing DDR chips running at 266 MHz and 333 MHz, like Samsung Electronics Co. (Q.SSE) and Taiwanese producers Nanya Technology Corp. (Q.NYT) and Winbond Electronics Corp. (Q.WBE), should be the first to gain from Intel's decision.
By ramping up production of the faster DDR chips ahead of their competitors, these companies will be able to catch the top prices for the chips while supply remains tight.
That's exactly what Samsung, the world's largest memory maker, is already doing. The South Korean chipmaker said it will ramp production of DDR-400 early next year, reaching heavy volumes by the second quarter.
"We expect DDR-400 to account for 30% of production by the end of 2003," said Jon Kang, senior vice president of product planning and application engineering at Samsung. "We've been actively working on it for the high-end desktop space." Codename: Springdale
According to companies in Asia, Intel plans to launch a chipset, code-named "Springdale," by the second quarter next year to connect its Pentium 4 processors with DDR-400 memory.
Computer gamers and others that use graphics intensive or memory-hungry programs - around 5% to 10% of the PC market - will likely be the first to buy PCs with DDR-400 memory. DDR chips are typically used in PC video memory - the circuitry that stores the complex images displayed on the computer screen.
Originally, companies believed DDR-400 would be a short-lived phenomenon, a bridge between slower DDR-333 chips, which are quickly becoming the main PC memory, and DDR-II, which uses a different, and more complex, architecture that is far from market-ready.
Computer parts makers have also reinvigorated efforts to develop motherboards, chipsets and other products necessary to connect DDR-400 to Pentium 4 chips.
"With Intel acknowledging DDR-400, that means the company needs them, or sees something ahead in memory chips that the rest of us don't," said one module maker.
Analysts say Intel needs DDR-400 to keep up with the ever increasing speeds of its Pentium 4 central processors.
Unfortunately, producing the fast new chips is technically challenging.
"There are heat problems with (faster forms) of DDR," said Crystal Lee, head of strategic marketing at DRAMeXchange, an online clearinghouse for memory chips.
Computer parts engineers in Taiwan say even DDR-333 chips have some problems with heat, and that speeds over 400 MHz could be too hot for use in current desktops.
Chipmakers have only recently found a way to beat the heat in DDR-400.
Samsung's Kang said his company has been able to reduce the heat generated by DDR-400 by producing the chips with 0.13 micron process technology. With circuits of just 0.13 micron in width - narrower than the current industry standard of 0.15 micron - electrical resistance is reduced, thus reducing the amount of heat generated.
Overheating memory chips can cause computers to crash. PC makers thoroughly test such parts before using them inside their products.
The fact companies like Samsung have found solutions to the heat troubles of DDR-400 may be the main reason the chip won Intel's backing.
Chris Hsieh, senior technology analyst at ING Financial Markets in Taipei, said the heat issues with DDR-II are severe enough to possibly delay the chip's market entry. Nobody is guessing by how long, but engineers at computer parts makers in Taiwan are shifting efforts to DDR-400 to ensure their parts work with the chips as soon as possible, and for as long as possible.
Right now, the industry group charged with developing DDR, the JEDEC Solid State Technology Association, is preoccupied with setting a new standard for DDR-400 so the chip can gain industry acceptance more quickly.
Currently, computer parts makers have to test each brand of DDR-400 chip individually to ensure it works with other computer parts - a time-consuming process. An industry standard will put everyone on the same page, and production of all the parts necessary to make a computer work with DDR-400 will move ahead.
Dew -
Because analysts’ ratings are a lagging indicator
Exactly! So what use are they?
9:12 (Dow Jones) Intel (INTC) and Advanced Micro Devices (AMD) should benefit from improving demand for computers, says Lehman Brothers analyst Daniel Niles. Improving corporate profits should increase business investment in hardware, especially as computer infrastructure continues to age, he said. He estimated 180 million computers are more than 4 years old. Niles upgraded Intel to overweight from equal weight and raised Advanced Micro to equal weight from neutral. In premarket, Intel was up 4.55% to $21.85, while Advanced Micro shares gained 5.56% to $9.50. (AEG)
Can you believe these analysts? Seems to me those computers were more than 4 years old a couple of weeks ago... Why wait until now to upgrade Intel?
EP
Spokeshave -
Have you brought *anything* of value to this discussion? Best I can tell, you seem most interested in trying to "catch" me in another semantic faux pas.
I think so. I've shown that there was no basis to your statements other than rumors and you repeat as fact the ones that support your biased views yet ignore the ones in the same article that contradict your positions. Prescott and 90nm are delayed until end of 2003, and Northwood will reach 3.4GHz on .13u. Both in the same article! One you embrace and repeat as fact, the other you reject and argue the opposite position.
You are a bit mixed up tonight.
EP
Spokeshave -
The Pentium 4 "Prescott" CPUs with 800MHz PSB, 1MB of L2 cache, Hyper-Threading II technology and manufactured using 90 nanometer process will be launched in the fourth quarter next year...
I can't help but think that if this was an artice on AMD you would say Q4, but seeing as it's Intel you say end of the year...
Another interesting point is that you are quick to believe that Prescott and 90nm are delayed until the end of 2003 based on rumors from what you consider "a reputable source", yet you reject this rumor on the same page from the same "reputable source".
To great surprise, now some sources report that the world’s number one semiconductor developer will provide 3.40GHz Pentium 4 microprocessors next year based on the Northwood core, again increasing the top core-speed of the chips made using advanced 0.13 micron technology
It would seem that you are very selective when it comes to believing your "reputable sources". If it makes Intel look bad you believe it. If it makes Intel look good you don't.
EP
Spokeshave -
But the link does indeed prove that I did not make it up, as you claimed.
Spokeshave, I made no sch claim. Your imagination is running away with you again.
EP
Spokeshave -
If the only thing you intend to contribute to the discussion is a critique of my semantics, please let me know, and I will quit responding. Regardless of whether I stated "90nm" or "Prescott" the fact remains that Intel, as recently as this summer, intended to have a 90nm product in 1H03. Now, no 90nm product appears on the official Intel roadmap at all for 1H03.
I am not simply critiquing your semantics, you are posting one thing then claiming you said another. You claimed 90nm was delayed to end of year and I see no evidence to support that claim. Furthermore, I see no evidence that Prescott has been delayed, other than a rumor posted on a tabloid. Now you are apparently saying that Intel originally intended to have a 90nm product in 1H03 but no longer shows that on their roadmap, this means a process delay. I am unaware of any such claim by Intel to have a 90nm product in 1H03, nor do I see the lack of a placeholder on the public Roadmap as proof that Intel will have no 90nm product until the end of the year as you claimed.
What it gets down to is this: You saw a rumor on the Inquirer saying that Prescott was delayed until end of '03. That rumor made the assumption that it must be because the 90nm process was delayed. You bought it without question. My point is that a rumor on the Inquirer doesn't mean it's true. That should be obvious to you by now.
EP
Spokeshave -
These were the issues that I said could be argued similarly for strained silicon and low-k. Incidentally, do you have some references to "the literature" to which you refer regarding the difficulties of using SOI? You clearly stated that there were many articles that speak of this. I would like to read some.
A search of google will give you plenty of hits.
Try "Silicon on Insulator"
EP
Spokeshave -
I am confused. Is Prescott not the first Intel product to be released on 90nm? But don't take my word for it. Go straight to the horse's mouth: [Link Delered]
I see no Prescott slated for 1H03
Yes you are confused about your own statement. You claimed End of '03 for 90nm. Not Prescott, you said 90nm.
"90nm has been pushed out to the end of next year"
http://www.investorshub.com/boards/read_msg.asp?message_id=603330
I have seen rumors of a Prescott delay, no comment on their accuracy. Even if true, Prescott <> 90nm. If there is a delay then Intel could use another product as a lead vehicle. Why not?
EP
Spokeshave -
Well, first off, I never said SS was of comparable risk to SOI.
I think you did. I called AMD's choice of SOI for Hammer a "hail Mary" and you said the same arguments could be made for SS. That says to me you were implying comparable risk.
With all due respect, I did not even attempt to quantify the risk of SS in even the most abstract terms. How is it then possible that I have exaggerated the risk?
"Every argument you presented can also be applied to strained silicon. Is that, then, Intel's "hail Mary"?"
http://www.investorshub.com/boards/read_msg.asp?message_id=603206
Spokeshave -
Prescott has been pushed from 2Q 03 to 2H 03. I don't have a link handy, but it is common knowledge.
Prescott's slip is a rumor from the Inquirer, but what you said was that 90nm had slipped. Another rumor, at best.
EP
Alan -
What's the meaning of Short loop and full loop.
EP
Spokeshave -
90nm has been pushed out to the end of next year
Link please? I haven't heard a word from Intel about this.
EP
wbmw -
since PowerPC worked so well with existing software
What existing software? I thought PPC replaced the 680x0 in Macs?
EP
Spokeshave -
I find it hard to believe that among all of the self-proclaimed industry experts on this board, nobody knows anything about strained silicon.
It is kind of surprising. What happened to Yousef?
Personally, I see it as Intel being able to do it so they do. That's much different from AMD who HAS to do SOI. What makes you think SS is comparable high risk? When Intel says they are going to transition to a new process technology I just accept that they will do it. When AMD says they are doing something very high risk I say I'll believe it when I see it.
I think you're exaggerating the risk of strained silicon.
EP
Spokeshave -
However, none of the above examples typifies the introduction of Itanium. Itanium was a new product for a *huge* existing market, but the product had a catch. It would not run any existing software well. Intel did not sell many Itaniums in the last year and a half because there has been very little industry acceptance to date.
Well you're exactly right. It did pretty bad. How can anyone spin it any other way? Itanium2 may do much better. It's not possible to do much worse.
EP
Dew -
the rumors are what I am most interested in. t.i.a. Dew
Well the rumors are that yields are terrible and binsplits stink, but take all rumors with a grain of salt. One thing's not a rumor. At this time, AMD is incapable of producing a competitive Hammer and this is 100% consistent with what you would expect to see if the rumors are true. That doesn't prove they are true though because there could be other reasons. It's just getting hard to explain it away in any other terms after all this time. Someone is bound to remind us about all the Itanium delays but Itanium was always on a standard process that was producing high volumes. Itanium was a totally new architecture and it took more time to work the bugs out. No other was to explain it. But Opteron isn't a totally new architecture. AMD has never produced a single product on this SOI process and it's hard to believe there's any other problem that would prevent at least a Clawhammer release, unless of course the performance is just too poor for release. This possibility should not be dismissed. AMD claims world leading performance, but what else are they going to say under the circumstances?
My personal guess is this:
Yields are bad.
Binsplits are bad.
Performance is disappointing.
Opteron suffers from the same process problems plus complexity issues have yet to be validated.
EP
Spokeshave -
OK, I will, provided that you make a case for AMD needing a "hail Mary" at the time that the Hammer design was announced. Times were a bit different then, and AMD was on top of the world. Hammer was by no means intended to be a "hail Mary" product - although it looks like it might be after all. Hammer was meant as a "gorilla killer".
I don't accept your premise. Nobody would take such a risky path unless there was no viable alternative. All the stars have to align perfectly to even have a chance. That's either an act of desperation or insanity and needs no further proof.
EP
Spokeshave -
It was finally released last year, and what, a few thousand units shipped all of last year? Is that a *real* launch?
Yes it was a real launch, product was available. It wasn't successful as a product though.
EP
Spokeshave -
Every argument you presented can also be applied to strained silicon. Is that, then, Intel's "hail Mary"?
Please make the case that Intel needs a hail Mary.
EP
Spokeshave -
Let's also apply your reasoning to Itanium, shall we? Since it was more than 10 years in the making
The joint agreement with HP was announced in 1994. It was released last year. I count 7 years.
EP
bababouie -
This is my opinion here - AMD didn't have the time, money or engineering resources. Hammer is just a souped up Athlon. Not a major revision to the core. They are integrating the memory controller, obviously not a big deal seeing as Intel did it years ago on Timna which was to be Intel's lowcost processor, and adding aHT channels.
EP
Dew -
I would appreciate any elaboration about AMD’s SOI process that led you to your conclusion.
SOI has never been done in high volume manufacturing. You won't find anything specific to AMD, other than rumors, but there are many articles in the literature that speak of the difficulties of using SOI. High cost, low yields and possible reliability problems are mentioned. AMD's choice was yet another hail-Mary attempt to field a competitive processor. So far it hasn't yielded a manufacturable product, however it was the only option AMD had. Had they relied on a conventional .13u process they would not have been competitive going forward anyway. When the plane is going down, even an unproven parachute is better than none at all.
EP
subzero
Please explain and elaborate, OK? Does this mean that memory accesses using the hypertransport (from adjacent CPUs) do not also access the extra ecc bits to perfrom ecc after the read operations are complet?
An aHT link is 16bits wide in each direction. For aHT, data integrity is maintained by means of a CRC at the end of each packet. Unlike a buss with ECC, if there is a bit error the entire packet must be retransmitted. With ECC, a bit error can be corrected on the fly.
EP
Elmer you should TM Phud these acronyms, I think there gonna stick.
Those aren't mine. I first saw them on the RagingBull message board.
EP
bababouie -
If you connect to a dual channel DDR-II and have 1MB L2 you make up for some of the shortcomings of an external memory controller. Isn't that what Intel is doing? Pumping up the FSB and dual channel? It seems to be working for the P4.
The P4's databus is 64 bits wide. aHT* is only 16 bits wide. Additionally you have no ECC and you use up one of Opteron's aHT channels.
EP
* "a" designating AMD HyperTransport as opposed to "i" in iHT meaning Intel HyperThreading
The below story says Fujitsu has no plans to merge it's Flash operations with AMD. Does anyone know what AMD's total Flash capacity is in actual units? I know they are limited to their F25 in Austin Tx and their joint venture Fab with Fujitsu. To my knowledge, Intel's only exclusively Flash Fab is F23 in Colorado Springs. Most other fabs also produce some flash. With recent news of increased Flash demand, I will be keeping my eyes open to see how Intel adjusts capacity to take advantage of the demand.
EP
http://www.ciol.com/content/news/repts/102112907.asp
Fujitsu, Toshiba tie-up on joint chip plant likely
With an aim to share the cost burden, Fujitsu and Toshiba are likely to enter in a strategic alliance to build a cutting-edge chip plant. A formal decision however will be announced early next year.
Reuters
Friday, November 29, 2002
Edmund Klamann
TOKYO: Japan's Fujitsu Ltd. will likely join with Toshiba Corp to build a cutting-edge chip plant, aiming to share the burden of increasingly costly investments, a senior Fujitsu executive said. A formal decision by the two companies, which announced an alliance in system chips in June, is likely by next March or April, Fujitsu corporate vice president Toshihiko Ono told Reuters in an interview.
Despite the tightening ties with Toshiba, however, Ono said his company, Japan's fifth-largest chipmaker, was not discussing combining chip operations with Advanced Micro Devices Inc, its long-time partner in flash memory chips. "There is no movement toward integration," Ono said, when asked about recent media reports that Fujitsu and the U.S. chipmaker would join their businesses in flash memory, used widely in cellphones and consumer electronics.
The plant under discussion with Toshiba would use 300 millimeter wafers, which industry executives say could give cost savings of up to 30 percent since they yield more than twice as many chips as the standard 200 mm variety. Japan's chipmakers, struggling to recover from last year's record losses, have been chided by foreign rivals such as industry leader Intel Corp for investing too little in advanced manufacturing, including 300 mm wafer equipment.
Pricey Plants
Japanese companies are finally moving toward the costly investments, which can go as high as $1.6 billion to $2.4 billion for a single plant, although they have tended to split the expense by investing jointly with their peers. Fujitsu's collaboration with Toshiba targets the fast-growing market for system chips, which combine memory, processing and other functions on one piece of silicon and are used to run a wide array of products from digital cameras to photocopiers.
The two gave an initial glimpse last month of how their planned cooperation would work, although it was short on specifics and focused on technologies such as encryption or video processing, or moving to narrower circuitry widths.
With AMD, Fujitsu has a joint venture in Japan that makes flash memory chips, used heavily in cellphones and consumer electronics, and the two cooperate in technology and development. "We often have meetings with them and discuss various matters on a daily basis," he said. "From the start we've had a division of labor....If we joined together, things would still be the same."
Media reports in the past two months have said Fujitsu was poised to merge its flash memory operations, which account for about one-third of its chip revenues, with AMD. AMD is the world's second-largest flash memory maker and Fujitsu ranks third, although combined they still fall short of sector leader Intel.
Ron -
Thanks. I see it now. These are options as stated in the article but they aren't purchases.
EP
Muell -
You can confirm that information here Elmer
I am registered and it shows no such confirmation on the insider page.
EP
Can anyone confirm the below information from the Inquirer?
Senior Intel executives buy millions of Intel shares
Do they know something we don't? Almost certainly, yes
By Cher Price: Thursday 28 November 2002, 11:27
FILINGS AT the Securities and Exchange Commissions site show a flurry of activity by Intel executives on INTC stock, on the 25th of November.
A heap of the senior suits got awarded stock options.
Andy Bryant, Intel's chief financial officer, exercised his stock options and acquired 528,852 shares on the 25th of November.
Robert J Baker, VP of the technology and marketing group, bought over 210,000 shares in Intel stock and paid the market price for the shares on that day, which was $20.23.
Sunlin Chou, the general manager of the technology and marketing group, bought over 260,000 shares at the market price.
Thomas Dunlap, the firm's pleader-in-chief, also acquired 260,000+ shares at the same market price.
Sean Maloney, the English executive VP of the Comms Group at Intel, bought over 529,000 shares at the market price.
Ron Smith bought over 260,000 shares in INTC.
Arvind Sodhani bought just under 200,000 shares.
Mike Splinter bought over half a million shares in Intel, paying the market price on the day.
And Les Vadasz, the president of Intel Capital, also bought shares – this time a sizeable 300,000 plus.
Something is afoot. These guys are showing great confidence in the Intel share price. The INTC share price closed on Wall Street last night at $20.90, modestly rising 3.47% on the day. µ