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Joe -
I realize that several knowledgeable posters have discussed this issue and perhaps the die is not so unduly large considering everything. However from a manufacturing perspective it is still very large and with the reported yield problems associated with SOI it will likely be a serious capacity hog, at least until the 90nm process generation.
HP to Ship First Itanium 2-based Workstations Running 64-bit Microsoft Windows XP
Partners and Technical Customers to Benefit from Volume Availability, Compatibility and Productivity
PALO ALTO, Calif., April 29, 2003
--------------------------------------------------------------------------------
HP (NYSE:HPQ) today announced the volume availability of its Intel® Itanium® 2-based workstations running Microsoft® Windows® XP 64-Bit Edition Version 2003.
more -
http://www.hp.com/hpinfo/newsroom/press/2003/030429b.html
Largest SGI Altix 3000 Supercluster Chosen for U.K. CSC
PRNewswire
April 29, 2003 (9:31 a.m. ET)
/PRNewswire-FirstCall/ -- SGI (NYSE: SGI) today announced a contract for one of the largest SGI(R) Altix(TM) 3000 superclusters to date, powered by 256 Intel(R) Itanium(R) 2 processors.
more - (long)
http://www.eetimes.com/pressreleases/prnewswire/72237
chipguy -
They recently suggested that Intel stored uP configuration info for things like enabling HT in P4s in on-chip flash. This is an absurd suggestion they seemed to have pulled out of thin air.
Really? Why is this so hard to believe?
Gollem -
Surely you can't be blamed for running code optimized for your competitor?
Nobody's blaming them. AMD is free to use any commercially available compiler they want. Intel is not obligated to provide AMD with the most highly optimized code.
Gollem -
True but official benchmarks can't be hacked. They must run straight compiled code.
Klaus -
Thanks.
kpf -
This board has not only a lot of people with sound knowledge but provides a clown to entertain them as well.
Well if you're going to get personal I can do the same. Too bad you lack the knowledge to understand the point. No, Opteron isn't just a warmed over Athlon but neither is Banias just a warmed over P3. There are major changes, unfortunately this is just over your head.
YB -
You're right, I read it wrong.
EP
Doug -
You're right. I missed where he said Call writers. Yes that would be bullish.
EP
YB -
Option writers are taking profit, instead of keeping those contracts in the wild until termination. Looks bullish.
Why would that look bullish? If they're selling them it's because they don't expect any more upside, no?
Gollem -
What I'm saying is why should AMD get a free ride on Intel's compilers? If the compiler checked the CPU ID and chose optimized code only for genuine Intel CPUs then I wouldn't have a problem with that. I'm not talking about compile time but run time. AMD has the option of developing their own compilers and they can optimize the code for their CPU ID.
If the compiler is checking if there is an intel cpu in the mistaken assumption that that is required to run SSE2 then the mentioned trick could very well be effective.
It doesn't have to be a mistaken assumption. It could be intentional and I wouldn't have a problem with that as long as it was disclosed and understood.
Gollem -
doesn't the compiler check the cpu of the machine on which you are compiling?
It could also check the cpu of the machine it's running the compiled code on, no?
Doug -
guess SSE2 support, 1MB L2, on chip memory controller, HT links, 64-bit extensions, improved branch prediction, and completely redesigned execution units don't cut it for you? :)
Please put my statement in the context it was intended. It was in response to another poster who said that Banias couldn't scale because it was just a warmed over P3. I could have posted almost exactly the same response to him that you just did to me.
Kpf -
However, I doubt Banias could scale much further, just for the reason it is a modified P3-Core (i.e. an architecture from the last century). Originally designed for 180nm, already shrinked once and blown in a third life for Banias. Now gets its fourth life for Dothan. From every experience we have, you just cannot do this endlessly.
You should apply that reasoning to Opteron, a warmed over Athlon.
Smooth -
They HAVE executed...
While this may prove to be true I think it is far too soon to leap to that conclusion.
wbmw -
I think that Intel will integrate a memory controller, graphics, or anything else when they have a solution that will allow them to ramp their manufacturing facilities without depending on the memory industry (which is what they would be forced to do if they have to respin silicon every time a new memory standard comes out).
Well that's a provocative statement. What are you suggesting?
fyo -
I can see how one might misinterpret my statement, but my understanding has always been that Timna was a great CPU - just sadly tied to a memory standard that didn't fit in the price range of the intended target.
I knew what you meant. It's just that others here might not.
EP
fyo -
Just imagine would it would perform like if they integrated the memory controller (although, after Timna, I understand their choice not to).
Timna was an excellent product and performed extremely well. It had no problems of it's own.
Semi -
Take some advice. Only a fool argues with a fool. Don't be a fool...
Semi -
O.K. Doug, So I expect that you will now "Raise The Flag" and "Call a Spade A Spade" about Dan's B.S. about vendors not using P4 in lightweight notebooks. I await your posting.
I posted earlier that I hoped there wouldn't be two different standards here, one for AMD fans and another for "all others". The person you mention has lied over and over again but always gets a free pass. Remind you of anywhere else?
Chipguy -
Just the Xeon full speed cache SRAM. Intel bought the chips for desktop Pentium IIs and IIIs.
I'm sure they did start out buying them but as I said, the quality was too poor and they didn't fully meet specs. If you understand test (and I suspect you do) then you'll understand the limitations of testing bulk commercial SRAMs. Sorry but I'll trust my Intel sources on this one. They owned the product.
Doug -
But they've already demonstrated Opteron runs fine at 1.55v, since at least some of the reviewed newisys 1.8 GHz boxes were set to that voltage.
It won't happen overnight. It's a long term reliability thing.
As always, with AMD I'll believe it when I see it. I'm still waiting to see if they can deliver meaningful volume or if this was a vapor launch. Yes they have a few for sale but they had long enough to build supply. Can they continue to produce them? We'll see I'm sure.
EP
Doug -
Are you sure about that?
No, not in this specific case. It was a rhetorical statement as oxide reliability is a limiter as you ramp voltage, that and heat.
Doug -
This probably means they could ship (at a minimum) 2.2 GHz back up at 1.55v.
Probably, and they can blow their gate oxides while they're at it.
chipguy -
The Klamath, Deschutes, and Katmai processors used commercial SRAM that Intel bought from specially qualified vendors for the module level L2.
Sorry to disagree, but that's not what I was told by the product engineers in Folsom. Maybe they bought some and I don't remember the mix but most was made in house.
Greg -
iHub does offer such functionality.
Bless you my boy!
EP
chipguy -
It [Intel] already is [in the SRAM business].
I know back in the PII days when Intel sold processor cards they had to make their own SRAM because the commercial ones were too slow and the quality was too poor but I didn't know they were still making them. You sure about that?
chipguy -
BTW, the McKinley L3 uses a highly dense hand designed sub-block architecture that Intel claimed was denser and had higher cell efficiency than the best commercial SRAMs.
Maybe Intel should go into the SRAM business?
DGagon -
But, since this person can't be civilized I say boot his ass.
There is a different poster here who constantly lies but nobody has suggested "booting his ass" because he is an AMD supporter. I would hate to see this board adopt two standards, one for AMD supporters and one for detractors. Many of us here have seen that on the SI site. I suggest you do what I do. If you don't like someone's style then ignore them. I only wish this site had the ability to ignore posts to that person as well as from.
EP
SZ -
Adding 64-bit capabilities increases the die size only 5% over the approximately 104 sq. mm that a 32-bit Athlon requires, using a 0.18-micron process, Lapinski said.
Yes, we know. You've said this about 3 times now but it does not address the addition of larger cache, memory controller and aHT ports. It is of note though that AMD was making this claim about a .18u process. Surely they should have benefited substantially from a .13u process shrink but you have not made your case. The only claim addressing the additional memory controller etc we have been able to document is AMD's promise of a 104mm2 A64. Has anyone seen anything credible about actual A64 die size?
Spokeshave -
I'm watching subzero's posts carefully. I'll jump in if it gets out of hand. Less moderation is better IMO, but enough is enough.
SZ has not used any profanity, no personal attacks and he has been on topic if not 100% accurate. I too would like to see him support his position with a few more facts but I can think of another poster here who has far less regard for accuracy. Let's not start a witch hunt just because he doesn't have the same opinion. If we wanted that we could go to the SI moderated thread.
P.S I know you've taken no action and you've done a fine job IMO.
Thread - Momentum seems to be growing for x86 emulation:
Red Hat warms to Itanium-booster plan
By Stephen Shankland
Staff Writer, CNET News.com
April 25, 2003, 3:58 PM PT
Leading Linux seller Red Hat is looking fondly at an Intel technology that improves the ability of the chipmaker's Itanium processor to run older software written for Xeon or Pentium chips.
The software, called the IA-32 Execution Layer, lets the new 64-bit Itanium processor emulate the two older 32-bit processors' workings. Intel says the technique is faster than the current, little-used approach of sluggish special-purpose circuitry in Itanium, endowing the forthcoming 1.5GHz Itanium 2 6M to run 32-bit software with about the speed of a 1.5GHz Xeon MP.
"Thirty-two bit support across 64-bit systems is important to Red Hat customers, and we are exploring ways to address this across the various architectures we support," Brian Stevens, vice president of operating system development, said in a statement Friday.
Intel's software is a module that becomes part of the kernel, or heart, of Linux, an Intel representative said. Red Hat Linux rival SuSE also will support the technology, and Intel has said Microsoft plans to do so with a Windows version.
Intel expects the software to make a debut in the second half of 2003.
Spokeshave -
You *do* know the difference, right?
It's just amazing to see the speed with which your mind works!
ChipGuy -
For starters, the IBM process uses a local interconnect layer, the AMD/Mot process doesn't.
Prior to SOI AMD used local interconnects. Are you sure they don't still use them, although it would explain why their cache is no longer as dense as Intel's (who also doesn't use LI IIRC).
Spokeshave -
This, as you know, has nothing to do with Opteron
You have an remarkable knack for spotting the obvious.
Tenchu -
In any case, with the amount of L2 cache traffic that goes on, combined with the huge processor-to-bus clock ratios, it's pointless to send speculative bus requests on every L2 access.
Makes good sense, thanks.
sgolds -
At no point did AMD ever promise a size for Opteron, they only gave an indication of how much 64-bit extensions would cost (5% of main logic).
They did promise 105mm2 for Clawhammer:
http://news.com.com/2100-1001-256556.html
"AMD disclosed that the first of several forthcoming processors, code-named Clawhammer, will be only 105 millimeters square"
Intel to open newest Hillsboro facility
Aliza Earnshaw
Intel Corp., the Santa Clara, Calif.-headquartered chip giant, will open its newest and most advanced development "fab," or fabrication facility, this weekend in Hillsboro.
Dedication ceremonies on April 26 will feature remarks from Oregon Governor Ted Kulongoski and Sunlin Chou, Intel senior vice president and general manager of technology and manufacturing.
Intel's latest Hillsboro fab cost $2 billion, and, at almost 975,000 square feet, could park three Boeing 747 aircraft. It is Intel's largest building in Oregon.
The new fab will manufacture chips from 300-millimeter wafers, and will initially develop chips at the 65-nanometer geometry. This places Intel "a generation ahead of the competition," according to Intel Oregon representative Bill MacKenzie.
The process used for most of Intel's chips today is 0.13 micron, or 130 nanometers. Intel has been developing 90-nanometer processes, and chip manufacturing at this new geometry will begin later this year. But as is typical for Intel, even as the company begins to roll out processors with the increased capacity that 90-nanometer geometry yields, it will be developing the processes necessary to manufacture chips with the still-higher capacities that 65-nanometer technology will deliver.
Intel now has 14,500 employees in Oregon, down from about 15,000 in mid-2002, and approximately 16,000 at the beginning of 2001. The Oregon site is Intel's largest and most complex site in the world, and much of Intel's most core research and development is done in Oregon.
sgolds -
So it is a qualitative (and performance) difference from the current 36-bit addressing scheme.
Thanks, I missed that.