Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
The right questions would concern GENERAL expectations, i.e. what has the market already priced in, as markets tend to be forward-looking.
Yes, Duke, I know :), hence my horror upon reading the phrase "median average"
That's fine-- it's that dreadful term I was objecting to.
WTF is a "median average" ?
Go for VNLADs or VNLAEs -- the extra year is worth the added time premium, IMO.
There are 2009 leaps available now.
He said INTEL, not AMD.
Yes, that was it. I wonder if RGood has anything to say about that...
I thought I saw something recently about Intel moving 45nm out from H207 to H108? What you said implies it is actually going in the other direction.
Can't find the "push-out" story I remember right now...
AMD claims they are using the first version of 65nm transistors on the last version of the 90nm products.
I don't think they claim this. What they mean, I believe, is that they share a lot of characteristics (materials, etc), (AMD says shared "technologies" or something), but the 65nm transistors may well have smaller geometry. At least that is my take on it based on what I've seen presented.
If G step were going to provide impressive power savings, I'd have expected AMD to brag about it last Thursday. They didn't. They said nothing about Rev G vs. Rev F in terms of power or frequency, and did not reveal those figures for the running samples either. Something isn't right.
AMD is just prioritizing schedule over features or performance.
There are no new features in Rev G over Rev F.
Because they will be behind in performance, I would've expected performance to be the priority, *if* they could manage it, although I guess they want to ship *something* by the end of 2006.
I do not believe the "volume" excuse that Dirk gave.
S1207 Opteron launch date slips at least 1 month:
http://www.theinquirer.net/?article=32188
...
The Rev F Opterons are now slated for August instead of July, and we are told that this new date is by no means firm, and may very well slip more.
...
No clock or power information were provided, but AMD *did* declare (from the podium, toward the very beginning of the presentation) that they had systems running 65nm samples on display.
They also claimed at some point that the samples were "production ready", and yet they did not announce any production wafer starts, and later said that the 65nm qualification process was continuing.
No claims at all were made concerning Rev G (65nm) K8 power & performance vs Rev F (90nm) K8.
The first 65nm parts (accoring to a roadmap DailyTech says was provided to OEMs in mid-May) will ship in December, and top out at 2.4GHz. Asked about this during the Q&A, Dirk Meyer said they were targeting the "mainstream DT" segment first with 65nm because that was where the volume was. (Not a very convincing argument, IMO.)
I think this all adds up to a large likelihood that not all is well with AMD's 65nm process at the moment.
The Inq doesn't realize that "Big Apple" = NYC, not New York State in general. :)
Get an E6600 in July...
Conroe XE 3.2GHz by year end, 2.93GHz XE at July launch.
http://www.dailytech.com/article.aspx?newsid=2625
Intel Confirms Two Upcoming Core 2 Extreme CPUs
90nm will be completely phased out by mid 2007
No, Fab36 will be only "substantially converted" by mid 2007, per AMD. And Sempron will not begin on 65nm until H207.
Dempsey is a CPU. Blackford is the chipset, which will also support Woodcrest.
it's up to AMD to coordinate with the providers
I'd have expected that Dell would be doing the coordinating here.
AMD is providing the chipsets, motherboards and chassis?
if they're going to supply Dell. Only 4S servers (Opti 8xx's), so production capacity isn't an issue.
If "substantially converted" referred only to Fab36 output, and not AMD's entire production, then you are correct, and the problems suggested by that info are really only 65nm tardiness (minor) and poor initial performance (major).
December OEM/ Q1 retail is kinda lame, but it's minor compared to the other issues raised by that information, if correct:
- 65nm top speed of 2.4GHz (DC) at launch in Dec/Q1, 2-3 speedgrades behind then-current 90nm speeds.
- 90nm parts (and so, parts in general for the first couple quarters of 2007, until 65nm can catch up and surpass 90nm speeds) get only one speedgrade bump beyond the 2.8GHz FX-62 due out at the AM2 launch, or shortly after. 3GHz FX is going to lose badly to Conroe XE, and a 2.8GHz A64 is going to lose badly to the 2.93GHz Conroe due out in Q4, despite the fact that the Conroe parts both use less power (even factoring in the IMC).
- Sempron 65nm starts in H207 (!) "Substantially converted" is sounding less substantial.
Again, all of this is true only if this information from HKEPC is correct...
Bankrupt shill says what?
AMD said that capacity was not an issue in Q1.
They certainly have held a performance and performance/watt lead over Intel for the past two years, but that seems likely to reverse over the next few months, and remain that way at least until the K8L. This is somewhat balanced by their increasing capacity-- their fortunes depend on exactly how far behind they fall in performance: if it becomes significant enough, Intel can successfully wage a horizontal price war across segements based on performance, as opposed to the vertical segment wars they have used in the past (e.g. expensive server & mobile, cheap desktop)
About 1 year from today was Groo's estimate for the first K8L parts.
You know, an Aceshardware poster suggested that a "Short DeMone Fund" which invested precisely contrary to what chippy recommended would've been quite profitable over the past several years.
That seals it. It is helpful to go back to some of wbmw's original errant claims, like this one:
http://www.investorshub.com/boards/read_msg.asp?message_id=11034627
The IMC is a wonderful contributer to performance on the K8, but it's not the primary one.
Bzzzt.
Why should I when we have a quote from someone from
AMD directly on the topic?
Don't want to answer, huh?
Uh no, people who invested in SGI took a calculated risk
with a turn around play with a large potential payoff.
Yeah, I got some penny-stock plays for you, too. Interested in those "calculated risks"?
I suggest you think of SGI as a big "payoff" for all your arrogance over the years.
Core2 has improvements that minimize the impact of longer latency to main memory. The flip side is that going to an IMC won't provide as large a boost for Core2 as it did for the K8.
People who invested in SGI are stupid. Now that we have you here, why don't you answer the question: Roughly what % of the performance improvement (clock/clock) from the K7 to the K8, on average (or break it down by categories of application) do YOU think is due to the IMC?
Which in practice means on average it provides much less
than 20% performance gain and in worse case probably
near zero gain.
Yeah, reducing latency to main memory by 2/3rds is nothing. And IPF is going to take over the world. And SGI is a great investment.
We're still waiting.
No, the K8's strong performance in games has mostly to do with the vastly improved average latency provided by the IMC.
Your link is not normalized for frequency. Now, go back, and READ the ENTIRE article I linked for you. It is OBVIOUS that the majority of the boost came from the IMC.
Again, you're pathetic. Again, another post worthy of pete. Congratulations.
Now, go read this, and it'll be obvious, even to you, that the IMC is providing the lion's share of the benefit:
http://www.cpuid.com/reviews/K8/index.php
In particular:
This test also allows to compare the memory latency, once the test exceeds the L2. The Opteron memory subsystem shows a 120 cycles latency, whereas the Athlon XP shows 360 cycles, namely three times slower, as the clock speed are the same. We can see here the effect of the integrated memory controller, that allows to minimize the request time to memory, and then drastically reduces the read latency.
pgerassi would be so proud of that post.
Yep, that and the "memory disambiguation" (allowing better load reordering), particularly for int performance.
Determining whether a load and a store share the same address is called memory disambiguation. Allowing loads to move ahead of stores gives a big performance boost. In some snippets of benchmarking code, Intel saw up to a 40% performance boost, solely the result of the more flexible way Loads get reordered. It is pretty clear that we won't see this in most real applications, but it is nevertheless impressive and it should show tangible (10-20%) performance boosts together with the fast L2 and L1 cache.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2748&p=5
We're still waiting for your admission. Let's stick to the subject at hand, shall we? That is: The performance increase of the K8 relative to the K7. Most of it came from the IMC, as AMD says. You were WRONG to suggest otherwise. Show a little character, and admit it.