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Hmmm - my own experience is that hyperthreading on Nehalem is very effective, a 40-50% boost in many cases. I can see where some loads might see even more.
Intel did almost everything right on this chip. The only areas where I would wish for changes for my workloads would probably have negative impact for more common loads.
AMD fans hoping that Nehalem would fall short of expectation should just get over it - didn't happen. Intel has put a strong product in the market at a good price point, and it will make AMD's ambitions to grow server share difficult to achieve.
beamer -
I'm not in the benchmark business and publishing my data would be a violation of my client agreements. In the testing I performed, Nehalem wins some, Shanghai wins some. I have said that I don't think the dynamics are likely in themselves to shift server share - those who chose AMD for specific workloads will probably stay with AMD, those who have an investment in Intel have every incentive to stay on that path.
During the course of my 6 month characterization of Nehalem and Shanghai, I got three refreshes of Nehalem, each better than the last. Raw performance is stunning and real world performance on many workloads is also very good. As I said previously, I saw performance between 170% and 200% of Harpertown in several tests.
But before we consign Shanghai to the dustbin of history, let's look at a few areas where it has an edge over Nehalem. Remember that big IT shops don't have the luxury of green field development very often, especially in these tough times.
One example is expanding existing virtual farms where peak loads are moved to faster machines and lower utilization loads are moved to less powerful machines. Loads are moved dynamically, based on usage prediction. So if you have say 10 servers in a pool and you want to maintain peak response as the load grows, ideally you add a few more high power boxes, move the critical loads to those boxes dynamically, which gives better response while lowering the load on the existing pool. While Nehalem looks like a good bet for peak load management, the problem is that you can't take your existing servers and pool them with Nehalem - the servers need to be in the same family (or the VMs need to be lowest common denominator, which defeats the purpose).
So the choice for Intel architecture in that scenario is Dunnington, not Nehalem.
With AMD, live migration is possible back to Barcelona and forward at least through the Istanbul products and probably the MCM product as well. Someone who has a mix of Barcelona and Shanghai servers not only has the architectural barrier (can't shift to Intel without replacing the whole pool), they also have a reasonable upgrade path, at least for the next year.
Core 2 was a pretty good product - so people who chose AMD over the last 2 years did so not based on raw performance, but because of something it did better than the Intel part, and Nehalem probably doesn't change that, at least in the enterprise space. For those doing a ground up project or fork lift upgrade, Nehalem is obviously a great choice.
re:lack of Cisco VPN support
You can use Cisco Anyconnect SSL client if your company supports it - runs under Vista64 and Win7 64
re: Does this mean that Larrabee has some capabilities of an FPGA
Larrabee is much more dynamic than that. Think of it as like a multicore CPU, but with many more cores, and the cores have special capabilities in addition to the standard x86 set.
Each core is based on the original Pentium design, literally. Added are x64 and a single super-wide 512-bit vector block which is well adapted to texture processing in a graphics pipeline, but can do other things as well. Each core supports 4 hyperthreads. There is hardware support for 16-way SIMD as oppsed to the 4-way SIMD on current products. Clock will be more than 1.5G, running to maybe 2.5G.
The memory architecture is much more like a traditional CPU than a GPU (which has small local memory), with decent size cache. Finally, there is a very high performance ring linking all the cores, which can also support dedicated fuction units to do special tasks - for example, a graphics implementation might have a rasterization unit for each core.
Initial implementations will be 16, 24 and 32 core. With hyperthreading, a 32 core can support 128 threads.
Another thought - Some folks speculate that Intel would integrate more complex GPU logic in combination with Nehalem style processors. I don't think that serves much purpose - an architecture with a big performance CPU and an array of flexible smaller units hits typical use patterns more effectively both for consumer and server loads.
I'm not dissing CUDA - but less accessable to developers is a huge handicap IMO
I was referring to next gen products - larrabee is a more basic building block in its parallel processing capability than what AMD (apparently) intends, but with a lot more of those basic units. While the total capability would be similar, larrabee gets there with say 80 units and AMD with maybe 8. AMD would probably have more raw parallel processing, but larrabee would be more flexible. At this early stage we are mostly comparing slideware, but Intel is an easy year ahead with IMO a better design. nVidia is not even in the game.
An example would be attaching 20 cores to do realtime transcoding, then releasing them so a different app would have resource to encode a disk transfer. In a GPU, what the cores do and how they do it is cast in silicon - in Larrabee, it is potentially up to the programmer who has use of the resource.
I would suggest that the reason nVidia is pushing for x86 capability is that they recognize the future is not in trying to program a graphics engine to do general purpose work. A dedicated team can do some cool stuff with a GPU, but about the time that a script kiddie can get 80% of the performance on Larrabee, CUDA will be just another footnote in computer history.
re: co-processing initiative that AMD tried to push
Not really. AMD's attempt to use HT for purposes beyond processor to processor, dedicated memory and I/O interconnect was, I think, an attempt to develop a low latency general purpose local interconnect. Displacing solid and well established protocols like Infiniband seems unlikely.
The key idea behind Larabee is that an array of processing elements can be assembled into configurations to do complex jobs including vector and other parallel processing, but using the x86 programming model. That expands the number of programmers who can use Larabee to pretty much anyone who can program in C or other x86 languages.
The first Larabee implementations are really demonstrations of what such an array can do. You could, for example, have a device which could configure the array to do high performance graphics, and modify the array depending on loading to also do complex realtime encryption of disk traffic or stack management of 10GB or 40GB network traffic. There are a lot of exciting possibilities.
But the real game changer would be to make that engine available in application space. With no need to go through the OS to attach computing resources, a much broader range of acceleration becomes accessible.
CUDA and openCL started as attempts to leverage existing GPU designs for non-graphics use. While it is possible to do stunts which show interesting performance, there are many constraints - most importantly, maybe one in a thousand programmers understands enough about how graphics processors work to make effective use of the resource. Substitution libraries which support standard programming models (for example math libraries) have unforseen consequences, since those models don't comprehend a completely decoupled resource.
Still, the work done on CUDA and openCL surfaced a number of issues that need to be addressed no matter what mechanism finally emerges to allow this kind of acceleration.
if larabee is 'pre-configured' to always look like a graphics card or something along those lines, no problem. but exposing the ability to do configuration on the fly is not something that can be done today with any efficiency. The second type of configuration is unlike anything Intel has done before, as it is not traditional multi-core - the cores are not OS resources at all. This is a pretty complex area. I'll be glad to go into more detail if you or others are interested.
Duke -
At the bleeding edge, the battle is around how to integrate the programming model with underlying parallel process engines. Larabee proposes a model with large numbers of fairly low power cores which have special purpose vector and other capability, identical in each core. The idea is that those can be assembled on the fly to do complex tasks with a virtual machine tailored to the job. Intel's process technology will probably make even a fairly large group of cores (say >80) fairly efficient, maybe <150W under load.
The AMD approach is to have an x86 front end to a more powerful parallel engine - fewer cores but with more power in each, and roughly the same TDP in total.
There are advantages to each approach, and we are probably years away from understanding how it will play out, since implementation is so dependent on the OS and other software to support either model.
What does seem clear is that nVidia is in a weak position no matter which way it goes.
The scenario I describe (live migration for peak load management) is important to hosted environments for a number of large users, not a niche. Outside of virtualization for internal use, this is the fastest growing area for virtualization. The particular application characterization set I just completed is for a 20,000 server deployment.
I agree with your conclusions though - customers currently using Intel servers will in many cases consider moving the virtualization loads to all Nehalem, and re-deploy older servers to other uses.
I've been working with both Nehalem and Opteron for several months. There is no question that Nehalem has great performance, and that for some workloads, it walks away from both Opteron and previous Xeon.
VMWare performance is very impressive, and I anticipate that some stunning benchmarks will be out very soon.
However, for other workloads, in particular virtualized SQL and some other virtualized BI loads, Nehalem's advantage is much lower, and in some cases Opteron has better performance. Also, at higher utilization (70% or more), Opteron uses less power - 30% less in many cases - to deliver similar performance.
Finally, live migration of virtual machines between Nehalem and either Opteron or previous Xeon is pretty much one way, unless you limit Nehalem to a harpertown/opteron subset, in which case Nehalem performance is hobbled. Some scenarios require migration 'back and forth' for peak load management, which would require replacement of existing servers with Nehalem.
Cisco is doing a green field development where they can avoid many of the issues which would hamper Nehalem. Clearly they have no live migration issues in an all Nehalem environment, and I also understand that they have a requirement to support many relatively simple loads rather than a few complex loads. It's a nice win, but I don't think it represents the broad virtualization market. For other users, the relative advantages of Nehalem versus Opteron will play out case by case.
EP -
Thanks for that info - the SEC document about AMD's development in 1992-3 http://www.sec.gov/litigation/admin/3437730.txt was pretty informative. Do you think there is still any x86 uCode in the current processors? The K7 was a pretty radical departure from previous designs. Remember I don't have much understanding of what goes on inside the chips, so I need it in simple language.
I think we are in a different world than that of the mid-90s. I was a MS shareholder at the time of the DOJ trials, but I was pretty sure they would end up on the short end, as they did. I also thought that was the right result.
Recent EU activity, both against MS and Intel, seems a lot less appropriate to me, but it also seems to be the trend. MS has caved on points where they seemed to have a defensible position. Their rhetoric seemed strong right up until they decided to give in. I wonder why they came to that decision? Does it imply anything about Intel's course?
EP -
Don't you have it backwards? AMD is saying it is a patent cross-license and that they are not infringing Intel patents. That seems clear enough, on the face of it. Intel may of course claim that AMD IS infringing, but that's a different issue.
I don't know the details of the agreement beyond what others have posted, but this approach to nuclear war can't be good for either company. I thought Intel would take up any claims after the deal was done, in order to avoid exactly the kind of interference claim now being made by AMD. Maybe they decided that after the AMD shareholder vote, they were on solid enough ground to go forward without that exposure.
I do know a bit about patent cross licensing in other areas - and generally, they do just amount to an agreement to not sue for infringement of the other party's patents. My understanding, which others here probably can clarify for me, is that AMD has not used actual Intel IP since the 286 days (edit - I don't know about any silicon process patents, I was referring to x86 design IP). I thought that the first agreement resulted from AMD's reverse engineering of 386.
That implies that what would happen if AMD was no longer cross-licensed is that AMD would be exposed to possible claims of infringement by Intel. It does NOT mean that they would be unable to produce their products. Even if there was infringing IP in the product, Intel would have to make a claim on that basis, after successfully getting the cross-license dropped. Even then, Intel would be required to offer that IP on a 'reasonable' basis, given their market position, much as happened to Microsoft.
There may be provisions for technology licensing in the agreement too... I'm not sure any of us know the details, although it looks like we may have a chance to find out.
I had early access as a part of the developer network program, but as others have stated, it was widely available in January. Once you are in, you get updates until release.
I'm running build 7044 which is pretty recent. Vista won't boot at all in under 512M and is a joke under 1G. The current Win7 is adequate at 512M. So that's a huge difference.
Vista ran decently for me on Core2 with 2GB, but many things about the operation were irritating. Win7 is MUCH better in that regard. While 'benchmark' performance may not be a lot faster, the OS does not get in the way nearly as much, and those mysterious delays that plagued Vista seem mostly gone.
There is still plenty of reason for those not on a budget to move to i7 - for example, rendering HD video is about twice as fast, and Core2 was no slouch in that department.
I have put Win7 up on a 1998 Compaq m300 with 384M (600 MHz PIII) - it runs better than XP on that machine. Performance on a variety of Core2 laptops is first rate. Looks like the memory footprint is less than half of Vista and the efficiency much better - especially the networking stack.
It looks to me like the minimum needed to boot Win7 is 350M, and on a small memory machine that goes to 250M once up.
Just when I thought I had a grasp on all the code names... can you or someone help me out with what is bulldozer? What I'm really asking is, how does builldozer fit into the landscape of products from AMD and Intel, in kind of feature - function terms.
or maybe Intel plans on acquiring Germany??
ya think maybe planning a few acquisitions a la cisco?
Sometimes, just having an enemy or a threat can help unite a company - but only if the response is to be better. Sometimes being better means finding a weak spot in the competition, sometimes it is disruptive innovation, sometimes just better execution. But that tactic can easily become poisonous.
I've done a little digging over the last few weeks on this 'attitude' and I'm a bit surprised at some of the extremism. Years ago, an engineer I had worked with for some time happened to start talking about his project to build a sustainable shelter, to survive the inevitable collapse of life as we know it when the one world order intentionally forced a global calamity. He was a good engineer but I had to wonder about his judgment after that talk. Of course, given recent events, he may be thinking that work was well timed...
I have seen Intel wield both the carrot and the stick effectively - but nothing compared to what I have seen from EMC or Oracle in sales tactics, or Microsoft in technology. Intel uses whatever they have to make their products the downhill choice - and they should. But there is always a choice. Great execution has always been their strong suit.
AMD's financial state is a concern, and I would hope that 99% of the company is working towards perfect execution, improved efficiency, and better understanding about how to build a sustainable value proposition. They have some interesting opportunities, but it is hardly blue skies.
re: The Gentlemen companies of the 80s basically went out of business.
Agree - and in some cases, that was sad to see. But while the business practices of some of the big players (Microsoft in particular) contributed to that, I think other factors played a bigger role, and that the older, slower models were just not right to survive as the business changed.
re: As an investor I want my company to fight for every design win, every socket on every board.
I agree completely. I would go further - business practices and regulations that attempt to prop up inefficient business models are bad for everyone.
It was obvious during the court proceedings against Microsoft that practices that were par for the course at the time were made to appear sinister in retrospect. One example was to mandate identical licensing for similar volumes in a market. That might make sense for soybeans, but in the complex interaction between the various players in the technology segment, it means that things like market-making for new products can't leverage a large business in a different product, because that would be 'illegal tying'. The result was not a better deal for smaller players, it was a worse deal for large players.
re: What a great way to treat your customers.
This would not be the first time. I know of several situations with Microsoft where AMD burned their own internal advocates in pursuit of the Intel jihad, in one case hauling a Microsoft exec into court to get him to 'clarify' some remark he made in private.
I know for a fact that Intel plays hardball - so does Microsoft, Oracle, EMC, to name a few. I also know that Intel has had a fairly rigid code of conduct for many years. That policy, like most in big companies, is designed to assure a measure of legal compliance - but unlike those policies at many other companies, Intel's has teeth and (with a few exceptions) seems to be pretty well followed. My personal experience with Intel is that you get everything you bargain for, and sometimes more.
We also have the example of RamBus, SCO, and others who seem to pursue their business model in court (I would also put RIAA in that category). Those folks are rightly regarded as pariahs, and any good will quickly evaporates.
The sparring between Microsoft and Sun was sometimes fun to watch - partly because I knew that the Ballmer - McNealy conflict went back to their high school days and had only a little to do with the companies they headed. But their efforts did not extend to the level where it distracted day to day activities - HotMail ran on Sun servers for years after Microsoft bought them. Microsoft and Oracle were also famous antagonists, but there were Oracle engineers on site in Redmond optimizing Oracle code for Windows.
Duke -
I have loaded Win 7 on a 10 year old Compaq M300 laptop with 384MB of RAM - boot is slow but once it is up it runs OK. A 512MB Thinkpad ran pretty well. Performance on both of those older machines is better than with either XP or Win2k (Win2K pro was the OEM OS for the Thinkpad) as long as superfetch and indexing are disabled. The minimum needed to boot is about 350MB. Sure 1GB will be much snappier, but it is not a requirement.
I found those posts to be interesting. It is pretty easy to skip past them if I don't want to read them. I also agree that it gives a different and useful perspective on the posters - you can get a pretty one-dimensional view without some off-topic 'color commentary'.
While I'm sure that these guys got the results they published, I have not seen any similar issues with the X25-E Extreme product. I suspect that the testers are using the X25-M in ways it was not designed to operate, and equally sure that it would not be a hard problem to correct.
Unlike rotating media, there is no difference in access time for any section of an SSD. The problem they describe comes from having components of a file spread over a very large number of physical locations - but that is exactly what you want to minimize hot spots and do effective wear leveling.
Performance of a flash SSD is only about twice the performance of rotating media for large sequential access in the best of circumstances. Where flash SSD shines is random access - and I doubt that even with the kind of abuse these reviewers applied, that the small block access was much affected. If we think about how a typical PC user would load a new disk, the operating system and application files would get laid down and not change much - so they would have good sequential speed. Anyone using a disk like that to save movies is wasting their money.
Some fairly minor adjustments to the leveling algorithm would make this 'problem' largely invisible, if it turns out that there is a real world use case that creates an issue.
Colin Lacey came to Unisys from HP, and to HP through Compaq. But he has a reputation as a careful team player. Chipguy's comments make sense here - why create demand that HP will fulfill?
Beamer -
re: Since you have compared performance of DRAM against Intel flash, have you also compared things such as power and cost?
Enterprise grade DRAM based SSD uses a lot of power. I haven't actually done the numbers but the ratio to flash would be huge - maybe in the hundreds. The cost for DRAM is about 25 times the cost for flash for a given amount of storage.
re:Do you have a link for this, or is it something you heard internally?
I have NDA information about the current state of next generation enterprise flash, but all the data I posted is publicly available. If you search "Intel Micron enterprise SSD" you will get a number of references. Intel and Micron work jointly on the base technology but are working independently on end product. The PCI-e work is Micron's direction. Intel's approach uses some very advanced SAN concepts (which explains their partnership with Hitachi). Both approaches get around latency issues inherent in flash and provide similar benchmark performance. Intel's approach, in my opinion, is far more advanced in systems architecture.
You can buy almost as much performance as you like in DRAM SSD - there is a 2U rack product which can deliver a million IOPS, but that box is about $500K. There are only a handful of installations that have the size and tuning to use that level of performance. 100K to 400K IOPS units are more common, but not more affordable.
re:So when do these drives hit the market?
My sense is that these advanced flash products will be available within the year, but the economy may change that.
Do you know if Intel is driving these designs, or someone else who is using Intel technology?
I'm sure Intel would encourage as many vendors as possible to use the base technology, but the products they are driving directly are not likely to be replicated anywhere else - the combination of technologies is challenging even for Intel and Hitachi.
re: Unisys is no longer a member of the Itanium
Solutions Alliance (ISA)
I had a conversation with a senior Intel exec around the time that Unisys decided not to continue with ISA. He told me that it was an understandable decision, because:
- Unisys had shifted heavily to a Microsoft focus (it was one of their 'growth pillars'), and was planning a big push around server consolidation especially around Microsoft Exchange. The only server app that runs on Itanium is SQL, which meant that continued investment in Itanium at the expense of optimized Xeon was not in their interest.
- Unisys had entered a joint development agreement with NEC which over a year or so would see all of Unisys manufacturing move to NEC. Therefore whether or not Unisys continued in ISA had little impact.
What is surprising to me is that performance of SQL on Itanium is better than on Xeon in most configurations. Since Unisys had both the largest MS SQL database instance, and also the highest transaction instance, both on Itanium systems, and they could presumably maintain an Itanium presence almost 'for free' through NEC, why not continue with a flagship product whatever the actual sales volume?
Excuse the late hit - let me clarify a few things.
My area of expertise is high transaction systems architecture. I started out in hardware - designing disk controllers, then array controllers. I went over to the dark side long ago, first in driver design, then query processor architecture, then higher level systems analysis. I can still go down to the metal in almost any area of database application.
I have characterized a lot of system components in the course of that work, I know a lot about how to talk to CPUs, how to optimize performance for various loads, how to measure results accurately. I know almost nothing about how CPUs or any silicon products are made.
My investments have been almost exclusively in tech, and I have done pretty well in applying what I see as trends in performance or usability as a proxy for how a company will do. But I moved almost my whole portfolio into real estate about 4 years ago, and have done little to use forums like this to fill in the gaps in my knowledge since that time.
The current economic situation seemed like a buying opportunity, and I have begun to build up modest positions in some tech stocks. I don't intend to come off as an expert in CPU design - just the opposite. If I lay out what looks to me like a trend and ask those who have a more fundamental understanding of the business to support or contradict my thinking, I would expect a facts based discourse. I didn't think that I needed to provide footnotes and links for the assertions I made - I just want to understand whether my ideas hold water or not.
It looks to me like you are picking at the way I am presenting, rather than discussion the underlying intent. It seems clear now, from posters who DID address my underlying assumption, that changes in the way CPUs are made mean that routine increases in clock, whether they were double in a year or two years or 50% in a year or 25% in 8 months, are a thing of the past, and that newer products will have a relatively narrow performance band largely determined by the process technology.
You also go for hyperbole - like ridiculously inflated vision of AMD's future clock speeds. I may not know how it's made, but I do know how to measure - and I have a straight from newegg AMD Phenom II 940 which runs 3.6G at stock voltage, has less than 100W dissipation (measured with a calibrated heat sink, not a guesstimate) after 30 minutes at 100% load, and temps at the IHS (as opposed to whatever the 'built in' sensor says) of 44C, which does not strike me as a dangerous level. From that, the idea of going up 5% in clock to 3.8G, or even 10% to 4G, did not seem out of the range of possibility. Perhaps it is, but that does not seem obvious to me even after some of the explanations here. Maybe it can't be done, but there is not much in any technology that can't tolerate a 5% increase in almost any dimension from a stable operating point. I would therefore assert that suggesting a 5-10% increase in clock speed from what I am running is at least a reasonable possibility, and no engineer with an interest in getting at the facts would claim it to be 'ridiculously inflated'. I don't question that you are competent in whatever your domain of expertise is - but you sure don't seem very objective, especially about AMD.
Even at the 3.6G clock, the AMD chip is slower and lower performing than a similar older core 2 part with the same kind of reasonable overclock applied. Maybe I should have said 'what if they release a 3.6G part' since I know that can be done within the published thermal and voltage numbers. But you would likely have some problem with that also.
re: I am starting to get the whiff of troll from your posts
Let's keep it clean. I was invited here separately by several apparently respected members of this forum. I have no ax to grind. You and others can make use of what I post or ignore it.
I would question your motives if I were not such a nice guy - I know several people who are running the Phenom II 940 chip at 4G on air with a 5% increase in vCore. That may not be something AMD wants to sell, but it is certainly not delusional, or playing games, to think that it could be done since it has been done. Your language is not designed to encourage a facts-based dialog - why are you so eager to squash this discussion?
I had a Conroe E6300 which was a 1.8G part. A little research now tells me that this was actually the low end of the launch, with the high end a 2.9G part. That throws a little cold water on my rough and ready analysis and lends some credence to the idea that significant clock gains are not as easy as in past generations, as suggested by wbmw and EP.
I think wbmw's read is informative - AMD could do higher speeds, but with marginal gains for a lot of work. I don't have the knowledge to evaluate how much effort those kind of things would take.
And re:
P4 nearly doubled clock the first year.
What universe do you live in?
Willamette came out at the end of 2000 at 1.4G and 1.5G. Willamette transitioned in 8 months to Northwood, which by January 2002 was at 2.3G, and by summer, 2.8G. So maybe that's not double in a year - I was going from memory rather than looking it up. I guess you could argue that P4 included a number of transitions, so the progression of P4 clock (which continued through the Prescott 3.8G HT parts) should be subdivided. But that probably doesn't mean an alternate universe, and it doesn't (in itself) make my analysis silly. The position that current technology makes similar gains unlikely today for either AMD or Intel seems more facts-based.
re: DRAM is NOT non-volatile.
No, it is not - but it has been made effectively non-volatile for a long time. Compaq / HP array controllers use battery-backed DRAM in array controllers to preserve write through, and have done so since 1996. Enterprise SSDs have used this technique even longer - at least since 1992. For the last 10 years, enterprise DRAM SSDs have gone a step further - redundant UPS and supplies keep the whole system up for several hours, then do a dump of contents to an internal disk drive before shutting down (or on command from host power management). This is 10 year old technology and ripe for plucking IMO.
I agree that the SATA link is a bottleneck for X25, and so does Intel - it was done for compatibility and convenience, and because SATA drivers are available for the target environment, which simplifies exchange.
The new design uses a PCI-e controller which uses disk semantics only at the highest level - so that operating systems and applications see the storage as a disk. Driver code is reduced from over 40,000 instructions and 4 interrupts for a SATA I/O to 2500 instructions and NO interrupts for the PCI-e card.
Internally, the flash is basically like 16 X25-style drives, which gets write performance up into the DRAM range. The combination of reduced driver overhead and reduced access time should get the product over 100,000 IOPS, maybe as high as 200,000 IOPS. There is also work on a 32 channel version.
As for fast tier-1 storage, the current technique of using drive firmware to limit the head movement to the outer tracks to reduce seek time also reduces disk capacity by a big factor. So the user pays for say a 146GB drive and gets 20G of storage - but pays the rack space and power tab (and drive cost) for 146G. X25 should be very competitive in that space just on price and performance, not even considering the power benefits.
re: Why bother with all the pre-loading and data management, when flash is non-volatile and can act just like a disk storage device?
The devices used for high transaction environments are a lot different than the entry level device in the comparison you link - they are non-volatile and have a lot of protection built in, including redundant memory which can survive multiple bank failures. Any extended power failure dumps to a built in hard drive. In addition, the data stored is transaction log or other data which is created when the database comes up, every time - so there is no pre-loading.
In write speeds for database transactions, the X25-E extreme shows 4000 random I/O per second at http://techreport.com/articles.x/15931/9 . A good 15K SAS drive does around 200 random I/O per second, and by limiting data to the outer tracks of a drive, that can be pushed to 500 IOPS - the X25 looks great compared to that.
The best enterprise SSD setups do 200,000 IOPS - so that's 50 times as fast.
The good news is that Intel and Micron are working on flash-based enterprise storage, and there's not much reason that can't get up in the range of the DRAM drives. There's no big technical hurdle - it uses current flash and PCI-e technology - so I would expect to see that product before too long.
I could see an extension of current 4 tier SAN to include X25-style flash SSD as a plug-in replacement for SAS drives, and the enterprise SSD as the high transaction rate store. That would be substantially lower cost than current best practice, and at least double the speed of the fast tier storage.
I'm looking at first silicon speed versus speeds a year later. P4 nearly doubled clock the first year. The fact that it went on to do a lot more doesn't really have much do do with speed optimizations to initial product. Except for heat dissipation problems, P4 might have gone up more, from what I have been told.
I'm not exactly a chip head, so I don't know what goes on in silicon design between initial release and subsequent revisions - but those patterns seem very repeatable. Probably many on this board could explain why it happens, but the data is 100% consistent (except for products which didn't stay active for a year). I don't understand why this AMD release would be any different.
Let's see how deep this fantasy is - Pentium II released at 233M, a year later it was at 450M. PIII released at 450M, a year later it was at 933M. The original Athlon released at 500M, 9 months later it was at 1G. Athlon XP released at 1.3G, a year later it was at 2.2G. P4 released at 1.3G, a year later it was at 2.2G. Athlon 64 released at 1.8G, a year later it was at 2.4G. Core 2 released at 1.8G, a year later it was at 2.6G.
It looks like the increase in clock rate a year after first product is lower now than in the previous generations, it still looks like a 30% or better clock rate a year later is routine. So a 3G clock going to 4G fits the pattern.
The numbers you suggest don't fit the pattern.
SSDs have been a part of high end transaction processing for a long time, at least 15 years. Most of those are high performance DRAM-based SSDs which have about 50 times the write performance of flash-based SSDs. DRAM-based SSDs are very expensive so they are used carefully. This is actually an area where we do quite a bit of work.
The cost and power consumption are not really an issue for those systems, since the SSD is a small part of the overall storage.
It's possible that in the near term, flash SSD may take on a bigger role for main storage. While their write performance is not dramatically better than rotating disk, their read performance is very good - and so applications like BI and other read-intensive jobs would benefit greatly. In that environment, the lower power consumption would be useful. The approach is to actively manage 'hot data' to keep it on the SSD, while migrating lower use data to rotating media. Most SAN management tools allow that migration to occur transparently to the application.