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I don't think AMD was under any legal obligation to call their extensions the same as Intel's. On the contrary I think they had to negotiate for the right.
But you can't really expect Intel to use the name AMD64 now can you? If they had continued to call it x86-64 then perhaps, but lets face it, that was a pretty poor name. Not easy to prononce, google for, use as a variable name, etc.
I meant running in long mode (ie with a 64 bit OS).
Of course in legacy mode you have all the things a CPU needs to be a real x86.
Nope. No hardware support.
See http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.html the system programming manual page page 13.
Both those require local drives on the 'diskless' computer (floppy or CD drives). There's no real need for that, and there's certainly no need to boot from the CD or floppy once you have finished installing.
Moving in the right direction though.
> But it's not 64-bit, it will be obsolete soon.
> Why the revulsion to an Athlon-64?
I wouldn't mind a 64 bit server too, but at my desk I don't want a chip with a slow fan, I want a chip with no fan at all.
Can't stand the wife's VAIO notebook. Noisy thing. Mostly it's the hard disk, but for some reason you can hear the CPU 'thinking' in the speakers even with the sound muted.
A fanless P-M on the desktop would be superb. I'd buy one to get rid of this slow fanless VIA CPU I have now.
Now if MS would get off their butts and support remote boot by PXE and diskless machines then people could have silent machines in their living rooms and servers in their cellars. I think there's a market, but you have to make it 100% compatible and no enterprise-level license fees either.
For that matter, if the Linux vendors would get off their butts and do the same I'd be happy. Linux can do diskless right now (I use it), but none of the distros have a clean way to install and upgrade a setup like that.
> You still don't get it do you? Intel isn't letting
> up on IPF in the least.
They've taken away one of IPF's big advantages: Being the only 64 bit ISA from the biggest chip co in the world.
That's letting up.
"IA64 won't replace established RISC
architectures because EPIC is a better processor technology. It
will replace them because it has a better business model (the
same chip merchant business model as x86) and the fact that Intel
is funneling those who need 64 bitness and/or muscular FP to IA64
rather than an extended capability x86.
http://groups.google.com/groups?selm=3DED4C30.3A49CF4D%40igs.net
That was true 14 months ago. It's not true now.
IPF still has the muscular FP of course.
I meant the changes relative to Northwood, not any Prescott-Nocoma changes (which would be minimal, bugfixing only).
I'm, sure they will extend it. An obvious place to start would be 16 bit mode accessible with the OS in long mode. Small differences in the BIOS and perhaps low level OS code are to be exptected too. Things like the way the IO-APIC work etc. No big deal.
On the other hand, extinguish is going to be difficult. MS do it with secret APIs, Can't see that working for Intel. Another way to do it is with patents, but again I think the AMD-Intel patent agreement will probably be extended to cover AMD64/IA32e.
In the past AMD have made noises about AMD64 not being covered by the existing agreements. Recently they said it was 'broadly covered' or some such.
Quite a turn-around for Intel. Bad news for AMD that Intel came to their senses so 'soon'. The good news is that Prescott is so underwhelming. The development of that line will be something to keep an eye on (of course).
The amount of redesign in Prescott is quite something. I know you keep hinting that we haven't seen the full extent yet, but what we have seen already looks like more differences than K7/K8. Just the ripping out of the half-cycle-latency 32 bit ALU and replacing it with a full-cycle-latency 64 bit ALU is quite a change in itself. And extending the pipeline by 50% goes way beyond what could be expected.
Nice of the Inq to correct their article!
> win-some, loose-some
Itanium doesn't have to win all benchmarks to have a market niche. But of course it will win all benchmarks that can scale to more than 4-8 CPUs.
> an opinion that heavily discounts theory vs. practice. My
> personal opinion is not as dismissive
Let's see how much contribution to the bottom line AMD gets out of respectively theory and practice this quarter, shall we?
> It's known that SUN is persuing > 8-way systems (of
> unknown architecture),
Is it? They aready have > 8-way systems of very much known architecture (ie SPARC), but I never heard of this before. Perhaps I'm out of touch. Timescales?
> as was Newisys (which I believe
> was explicitly SMP, but I'm not sure.)
Pretty sure you are thinking of the 32 way cluster (ie not SMP) stuff.
> [changes in Itanium implementation] implies a change in the
> toolchain/software
Not if they just increase cache sizes and MHz and SMP width.
And even if they do need to change the toolchain, so what? I don't think it's such a big deal for their target market. Some of them compile their own, others can just install a newer version of Oracle or the JVM. This isn't the games market, where a newer version of Quake III won't be released.
> it's undoubtedly true that there is a high-end class of
> CPUs that hasn't yet been encroached upon by a commodity
> product yet
> Well, I (explicitly, in my last reply) don't consider
> Itanium to currently be in that class
Well who is then? Hint: Itanium has the record in a long string of high end benchmarks right now. And I'm not just talking about artificially-limited-to-4-way versions of those benchmarks.
> AMD may be 6 months behind _introducing_ 90nm product
And they may be more. AMD's record in actually introducing transistor sizes isn't too hot. Nor is Intel's, but in this case their product is out there right now, so that's something concrete not based on speculation.
Even if it's only 6 months I would classify that as 'way behind'. These process generations aren't that long.
> what the heck are we using 64-bit processors for
> if not large-footprint applications?
You seem to be saying it's silly to use 64 bit processors for applications with a footprint of between 1 and 6 Mbytes. By the way, footprint is something of an oversimplification. Lots of apps that touch more than 6Mbytes of data can benefit from a 6Mbyte cache.
> Hammer provides superior glueless scalability to a point,
> and 'gluey' scalability is technically feasible and
> competitive, but as of yet undemonstrated.
I guess so. But undemonstrated technology doesn't tend to sell well, so right now Itanium has an advantage here. I'm not quite sure whether the Opteron cache coherency protocol needs updating in order to do the high way glueful SMP, but I suspect it does.
> Red Storm will be a good first peice of evidence for
> performance in the "gluey" domain.
You really need to look up Red Storm and how it works. It's nothing like SGIs 128 chip Itanium machines with their cache-coherency, unified OS and process migration. It's much more like a cluster of independent uni(!)processor machines with a fast network between them. Think Beowulf magnified.
> [on the question of how easy it is to speed up Hammer fp]
> You're reaching
I think IA64 is the better instruction set for Fortran codes. It don't think that's all that controversial actually. Even AMD wanted a 3-operand format for TFP originally and there's little doubt that you can't have too many registers in this area. And that's without the rotating registers stuff which seems to work nicely for them even if it does seem a bit clumsy.
> The FP execution unit, instruction decode/dispatch,
> and register utilization (decoupled from the ISA
> via register-rename techniques) are probably the
> simplest of any capability you might wish to add to a CPU.
Well I'm not a CPU designer, but I don't get the impression that these things are so simple. In particular dispatch is a major headache in an OoO processor.
> Given the choice between optimizing a custom application
> for your 128 cpu Itanium SMP system, and optimizing a
> custom application for a 256 x 2-way Opteron cluster
> with high-speed interconnect (blindly assuming equal costs)
> and taking into account the more "conventional" programming
> model of the Opteron cluster, my personal choice would be
> an easy one
You really think so? In the SMP case you have shared coherent memory, very fast communication latency (perhaps 100ns instead of 100us) and you can for example use the threads that C++ or Java provide, or use an autoparallelising Fortran compiler. That seems like a conventional programming model. In the cluster case you have large latencies and you have to structure your app to handle them, plus you have to reduce all communication to message passsing using some message passing library. No shared memory, no low-latency queues and semaphores, no threads that migrate to whichever CPU is idle. That's what you'd prefer?
> it's undoubtedly true that there is a high-end class of
> CPUs that hasn't yet been encroached upon by a commodity
> product yet
Well, then we agree; why all the protests?
I originally joined in to this thread as a response to the idea that Intel couldn't make CT fast enough to compete with Opteron without making it so fast it beat Itanium II. You seem to be agreeing that Itanium is in a high-end class where CT and Itanium can't encroach, so that's not a problem for Intel.
I agree that the trend is in favour of the up-moving commodity chips rather than the high end chips, esp. if the high end chips don't want to move to the high volume area.
> Intel didn't have larger on-chip caches as a rule
> until the PIII Xeons
I think you are forgetting large-cache PPros (OK it was off chip, but nevertheless it was impressive and not something AMD was delivering) and the HPPA 8500 fabbed by Intel.
> Let's start by recognizing that this scenario inherently in
> corporates a period of time between now and the introduction of
> said hypothetical Itanium.
You can get a large cache Itanium now. When the larger cache Opterons and CT chips arrive there will likely be a larger cache Itanium to go up against it.
> AMD's 130nm SOI process is just really beginning its
> volume ramp right now [...] AMD's ramp of 90nm production
> is imminent
There's always some process being ramped up, isn't there? And AMD always has larger area/Mbyte and smaller total Mbyte caches than Intel at the high end. Perhaps they can turn that around at some future node, but right now they are way behind on moving to 90nm and that is a obvious disadvantage in terms of cache density. So I'm going to assume Intel's advantage in cache is going to stay until I see evidence to disprove it.
> [Hammer needs smaller caches]
True to some extent, but there will still be lots of code that works better with a 6Mbyte cache than a 1Mbyte cache.
> Hammer scales better
This is rather hypothetical given that you can't get Hammers with more than 4-8 way and you can get 128 way Itaniums. Yes, Hammer scales better moving from 2 to 4 CPUs. After that Hammer hits a brick wall also known as a primitive cache coherence protocol.
Of course most of the money is in the 2-4 way space.
> [It's hard to add FP performance to Itanium]
Well, they are well ahead right now on SPECfp-like codes and I'm sure the next version won't change that. They have the ISA on their side. (They don't have the ISA on their side for integer workloads, there they only have the cache and the compilers on their side.).
> [It's easy for AMD to add more FP performance to Hammer]
Sure, but whenever you increase the issue width you risk reducing the maximum MHz and you risk running into diminishing returns because you don't have enough registers.
> [Opteron has more bang/buck]
Probably true, but sometimes you just need more bang, and the bucks come in second line. I already addressed the scaling argument. Remember that when you have a 128 chip Itanium SMP they are not all on the same shared bus!
> By unifying the commodity and high-end product lines,
> means that AMD can tackle both markets and reap the
> crossover benefits of high-performance at commodity prices.
Absolutely, but when you say high end you have to realise that there's a higher end above what Hammer can reach right now (or in the near future) and that is where Itanium and Power are duking it out and noone else need apply. Not Hammer, not SPARC, certainly not Xeon.
> imagine Intel will sacrifice the entire Xeon market
> and continue to push IA-64 alone. A nice fantasy, but
> not realistic.
It's what I was hoping for
Anyway who knows how far CT is from market introduction. How long from Hyperthreading was announced till you could buy it?
Intel's advantage is that they can make large caches that are still manufacturable and they don't even take up that much silicon. That allows them to find a niche for the Itanium. They couldn't do that if AMD were better at caches, but they are not, so - advantage Intel.
On the other hand, AMD made the right tactical decision regarding instruction set so - advantage AMD.
It wouldn't be interesting if one of them went bust.
I'm long AMD again by the way. Just in time for CT to destroy AMD's biggest advantage...
> I'd love to know how a Yamhill chip is going to steal an
> Opteron sale, while performing so poorly that it doesn't
> impact Itanium sales...
By giving Itanium very large caches and very fast fp performance they can give it a performance profile that is unattainable for AMD64 with it's instruction set disadvantage and unattainable for AMD with their apparently limited ability to make very large caches yield well.
On the other hand I don't think that the market thus opened up to Itanium is large enough to support the development effort needed to keep it ahead of the game. So in the somewhat longer term its future is very much in doubt.
But even before Yamhill became/becomes official there was never a credible effort from Intel to push IA64 into high volume markets, by which I mean a million per quarter (3% of the x86 market size?). Certainly a few 100s of SGI machines isn't going to cut it, even if they pack 128 CPUs per machine, which I bet they don't on average. It's all rather reminiscent of Alpha as far as I can see.
Actually quite relevant:
Intergraph may sue AMD over Clipper patents
http://tech-critic.com/comments.php?id=8645&catid=1
I think you mean The Register?
Sun buys Opteron shop "Kealia"
Somewhat confusing article from El Reg:
http://www.theregister.co.uk/content/7/35468.html
Awesome web page: http://www.kealia.com/
"[Brookwood] claims the Prescott's 64-bit extensions are different [from AMD64], and Intel won't implement it in this chip, but rather wait until the Tejas *T recension, which is supposed to arrive next year."
http://www.theinquirer.net/?article=14036
Are the dark transistors implementing a 64 bit instruction set.
What instruction set could possibly be that big? IA64?
You can get 64bit Java for Itanium right now:
http://java.sun.com/j2se/1.4.2/system-configurations.html
It's just the 1.5 beta release that is a little late for Itanium.
> And 939 pins? What is up with that?!
> theInquirer has gotton inaccurate to the point where it is more > misleading than enlightening
Well, the 939 story came true, as they often do:
Here are links to the pictures of real live Socket 939s. And they even have 939 pins, so they live up to the name.
http://www.theinquirer.net/?article=13970
> It´s up to INTEL to choose the mix
So their transition to 90nm is so smooth they just flick the switch when they feel like it?
What do you think is Intel's main product for 2004? Northwood or Prescott?
Not only did they launch on Superbowl day, but they moved the NDA expiry to Superbowl day at the last moment. A Sunday. See Johan comment on Ace's message board to this effect.
Very disappointing so far. I wonder whether the problem isn't heat after all. Sure, they could probably cool more than 103W but would DELL want to cool that much? DELL put a lot of effort into their cheap quiet reliable cooling which uses just one fan for both CPU and PSU. Perhaps DELL insisted that Intel not launch a chip before DELL had worked out how to cool it without revamping the whole PC.
If they get the heat issues under control I'm sure they will be able to ramp the MHz to ridiculous levels.
The nice thing for AMD is that their Quantispeed ratings probably won't need recalibrating because of Prescott. One worry gone.
Thanks Not sure I'm back really. This place is very time consuming!
Perhaps this has already been posted here (I'm very out of touch) but I thought the Prescott figures from computerdiy.com.tw were rather interesting. Linked from http://www.theinquirer.net/?article=13783
Note how the integer benchmarks are somewhat slower at the same MHz while the fp benchmarks are much faster. I wonder if this means the multiple clock speeds in the P4 core have been got rid of. Ie the integer part could be running at nominal speed instead of double and the fp part could have doubled its throughput instead of having a 2 cycle latency on most operations.
If you already discussed this to death please ignore me.
how much trouble Athlon chipset makers had with much lower data rates on the point to point EV6 bus"
Did they? The main trouble I could see was that AMD kept changing their minds about what speed to run at. I think with an agressive but predictable roadmap there would have been no trouble.
The question is, can one CPU address the memory of the other in a transparent-for-software way.
The other question is, is the memory cache coherent.
The next question is, does the link have a latency that is of the order 100ns or of the order 100000ns.
Here are some quotes from your post that you didn't highlight:
Even the Pentium 4 Extreme Edition can't quite keep pace with the FX-51 and even the more mainstream Athlon64 3200+ in most games
In general, the workstation applications that are well optimized for SSE-2 and SMP/multithreading perform best on the Pentium 4. Most other applications in our benchmark suite seem to run better on the AMD64 family.
Haddock, it's funny to see the same people
I suggest you address such comments to the people concerned, not to me.
"there's only one Hyperthreading Pentium 4 Extreme Edition chip in the country"
http://www.theinquirer.net/?article=11759
In edit: The AthlonFX seems to be in stock some places, eg Newegg
http://www.newegg.com/app/viewproduct.asp?description=19-103-414&refer=pricewatch
But there aren't a lot of them about. www.alternate.de doesn't seem to have them.
Not as nicely as the 939 pin version methinks
2.8 GHz Athlon 64 FX tested by Ace's:
http://www.aceshardware.com/read.jsp?id=60000268
Prescott Hyperthreading is 2-way
And LaGrande is implemented as a virtual PC (VMware-like)
http://www.theinquirer.net/?article=11579
Intel's answer to the Athlon 64 FX
Broken link: Try:
http://groups.google.com/groups?selm=e8bw7DreDHA.3216%40tk2msftngp13.phx.gbl
Sounds a poor excuse for crashing software.
let alone let them count the number of die, as well as measure the die size to the nearest tenth millimeter at less than 3% accuracy?
If he was able to count the dice then he didn't need to measure the die size, did he? He says the width was between 8.85 and 9.35 mm. That corresponds to between 21.39 and 22.60 dice from edge to edge. Ie there were about 22 dice from end to end.
It's not an unreasonable accuracy from a quick visual inspection.
Of course, you can choose not to believe him. There's no way he can prove it.
That is all supposed to be exceedingly sensitive information.
Didn't an Intel exec hold up a wafer from R&D for journalists a few years back, after which analyses of the photos were used to give a good die size estimate? So sometimes sensitive information leaks out.
at least give a reasonable explanation for how you came in contact with this material.
It seems to me that if the explanation he has given us isn't the right one then any alternative explanation can only be one that gets him or his source into more trouble.
So on laptops with integrated graphics this means the graphics processor has to go through the northbridge memory controller to access DRAM.
Yes, but the graphics processor and the northbridge are on the same die.
On a mobile A64, it would go through the memory controller located on the die.
A different die to the graphics processor (unless they put the GPU on the Hammer die!).