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wbmw,
Not to say it's impossible, but we will probably see Fusion before we see integrated CPU graphics from Intel, and I think the reasoning is simple. If you are going for the best performance in a given power constraint, and your power constraint is fixed, why would you want to share your compute element with graphics?
For the same reason you share it with the memory controller: On the net basis, you save power.
BTW, north bridge dissipation is not free. It has to be accounted for. Also, performing graphics in the northbridge may run into thermal problems, require larger heatsink or even additional fan. It is cheaper to dissipate a little more heat from the existing high performance HSF than to add a secondary one.
Joe
wbmw,
This is not an ecosystem. It's like seeing 2-3 oceanic objects, including one fish, and calling that an aquarium.
I would agree that Torrenze ecosystem is not there for the entire server platform, but of HPC market, with limited number of participants, it's pretty much as much as one can expect.
Joe
wbmw,
Based on what? Maybe there is a miscommunication between what you consider an ecosystem, and what I would call an ecosystem. Do you see a wide range of accelerators that can plug into HTT today, for example?
I think there are 2 to 3, and one of them plugs directly to the CPU socket.
Do you see optimized software libraries that address the latency penalties in software for transferring executable code to an off-chip processor?
I am sure the copanies selling these accelerators have libraries for them. As far as programming details, I don't feel like investigating.
Joe
Klaus,
What I mean by modular is the way dual core (or multicore) CPUs are modular. Each core is almost a standalone module (core) plugs into an on-die infrustructure. It plugs into the System Request Queue.
By modular graphics module, I would expect GPU to be standalone, self-contained GPU processing engine that plugs into on-die infrastructure for memory access and I/O.
What I meant by integrated would be a merged CPU/GPU core, with number of processing pipelines that can interchangeably process graphics related or CPU related instructions.
That would certainly be a huge undertaking, and a very risky one. Stretching the schedule (ETA) of the Fusion chip could either mean waiting for appropriate process technology, or there is an outside chance of some more ambitious project with some integration in mind.
Analogy here would be the way FPU started as a separate chip, moved to somewhat clumsy x87 FPU, to SSE with more direct communication to the between the registers.
Joe
Keith,
You can´t expect to do nothing for a whole year and still thrive.
Not even the 2.8 GHz server part moving down from SE category to normal one (like the desktops), with corresponding 3.0 GHz in SE category...
Joe
wbmw,
Is this Fusion, or something else? I don't think you would expect this micro-architecture within a year of Barcelona, so that puts it in 2009 at least.
That's what my guess would be. So it will obviously trail Nehalem in time to market.
Joe
wbmw,
It will be in some workloads, but not in everything. I think Intel is doing all they can by making the next Xeon MP chipset connect to all the CPUs via point to point FSB links.
That should certainly lessen the bottleneck. It is going to be a monster chipset with 4 FSBs and number of memory channels.
If they can get this ramped up and with enough options by then, but I really doubt they will have this ecosystem ready
I think the ecosystem (for Torrenza) is ready. And while I wish I could see some general market potential for it, at the moment it is really onle a purely HPC play.
If it grabs a hand full of large installations, great, but it still won't contribute to sizable revenue amounts for quite some time yet. And I wouldn't count Intel out of this market, either, especially with them opening FSB licensing in the short term and moving to Geneseo in the long term.
HPC market is small when looking from Intel point of view, but when looking from point of of much smaller company (AMD) it is more significant. As far as Intel opening FSB, if I were to invest money in Intel solution, I would invest it in CSI, I would not waste money on soon to be discontinued FSB.
Joe
mmoy,
Core 2 has some significant SIMD improvements that have put it
ahead in multimedia performance. Even if you can process FP more
quickly, you still have to do load/store.
Do you think that Barcelona will have insufficient resources for that?
Joe
Klaus,
yes. But probably not in core-µarch. Rather next integration-step. Makes more sense.
I seem to recall seeing a new micro-architecture on some roadmap. I thought it was originally scheduled for 2008, but it is no longer on public 3 year roadmap, so it could now be 2009. Hester mentioned it in an interview as well. I don't know how exactly it relates to Fusion, if they are thinking a deeper integration between graphics and CPU, or a modular approach. I would still assume that the approach will be modular.
Joe
wbmw,
I think the results (segment-wise) are what I would expect. Intel gained share in performance-sensitive parts of the market (servers), very likely gained in high end of the desktop, but lost big time in areas where people couldn't care less about the performance (notebooks, mainstream to low end desktop).
Joe
Keith,
Fourth quarter microprocessor unit shipments grew 26 percent year-over-year and 19 percent sequentially as customers continued leveraging AMD solutions to provide greater choice to the market.
That looks like a significant unit share gain for AMD. Too bad that ASPs sucked.
Joe
wbmw,
I wonder what AMD's plans are after Barcelona. I wouldn't expect another major micro-architecture change in time to compete with the next Intel onslaught.
K8L is a relatively minor micro-architecture change compared to Piii -> Netburst -> Conroe. Major one is upcoming after that.
Joe
wbmw,
I think AMD will try to target SPECfp_rate and certain HPC apps as if they were the Achilles Heel of the Xeon MP platform.
Well, the FSB is stell a weakness for Intel. Another tool AMD has (will have) in HPC market is Torrenza. Combination of strong FP capabilities, native quad core, low latency, high bandwidth memory, glueless design and Torrenza make a for a pretty strong arsenal in the HPC market
Joe
chipguy,
In many areas NGMA is way ahead of
K8 (bioinformatics and EDA for example) and more raw FLOPs
isn't going to help much.
Barcelona is going to get some improvements on the integer end of things as well. I don't expect it to beat Conroe in IPC, but it should narrow the gap compared to K8.
Joe
wbmw,
And quite interestingly, too, since very few high end scalable server apps actually use floating point.
That's a good point (very few). But Barcelona may solidify AMD in the HPC market.
Another variable in the equation is that there are some code sequences that can be optimized through vectorization, and I am assuming that these SSE(2) instructions gain parformance proportionally with FP.
Maybe the improvements there can help Barcelona overcome Conroe's (general purpase) integer lead.
Joe
mmoy,
Any idea as to what was in that stepping?
No new functionality. Generally, just improvements in power or performance characteristics. Or, potentially, bug fixes.
Joe
wbmw,
I happen to think that AMD has bitten off more than they can chew with the announcement of 6000+ chips, and they simply aren't binning enough.
Did you mean 5600? I don't think 6000 has been announced. It was on some roadmaps, but I don't think it has officially been announced yet.
I think the new stepping (from Reseller Mike's list, CZ steping):
http://www.investorshub.com/boards/read_msg.asp?message_id=16374966
improves bin splits somewhat, and 5600 parts seem to come from that stepping. But, it appears this stepping was put into production later than originally scheduled (what else is new?). Therefore, it appears that only a small number of parts from this stepping are available at this time, allowing only 5600 parts. I think that once we see the crossover from CU to CZ parts on mainstream parts, AMD may have enough parts to launch 6000 parts.
I don't know if my reading of the part numbers is right, but it seems that the 90nm parts start with C and probably, 65nm parts start with D. So AMD is simultaneously switching the 90nm K8 parts to CZ and 65nm parts to Dx.
The volume parts are still 90nm. It will be interesting to see next week's list, to see if the parts due 1/27 arrived. Or, actually, the price list 2 weeks from now, since 1/27 is Saturday, and I doubt these will show up on Saturday.
AMD's plan appears to be to move to get performance parts from CZ stepping and mainstream parts from Dx. We will be able to measure progress from Mike's list.
Joe
wbmw,
Actually, I made a mistake, I should have said that AMD added 1 HT link. There are going to be 4 HT links vs. 3 (that fit into 940 package) and Socket 1207 apparently will be able to use them. The difference between the pin counts is more than 1 HT link.
Further, it seems that there is some forward compatibility built into the sockets. The HT3.0 very likely and possibly DDR3. Another component that can eat pins that will make it into future mobos and CPUs is spearate voltage plane for the memory controller. That is certainly going to consume extra pins, but don't account for any power delivery differences between current Socket F and Socket AM2 (the split voltage is not available for current processors).
Joe
Keith,
Think volumes. A few thousand chips at best are required. But the volume for Opterons and A64 X2 is another matter.
Low volume (available for sale) has not exactly stopped AMD from introducing 65nm or 5600 processors...
Joe
wbmw,
Socket-F has more pins, which may allow better power delivery characteristics, which enables higher speeds. Just a thought.
I am not sure if Socket-F has more pins for power delivery. Most of the extra pins are there for extra 2 channels of HT.
Joe
Keith,
You mean up to 5000+? The 5200+ is 90nm. I probably misunderstood what you meant.
Yes, sorry, I meant 5000.
True, AMD can´t seem to get higher-clocked models out of the door. The 6000+ should have been available in Nov/06.
Weird thing is that the FX-74 (3 Ghz) is available. I don't know what the hold up is with 6000, since, other than the socket, is the same chip.
Joe
Keith,
AMd is now selling Energy Efficient (65W) desktops for the same price as the older 89W. Up to 5200, which has not been available (probably since it is supposed to be 65nm part, and they have been extremely slow to arrive).
Well, other than list prices matching already available street prices more closely, not much is happening with AMD. 5800 and 6000 still not available, 5600 seems still limited to big OEMs.
Joe
alan,
Good point about rapid speed grade introductions. What remains to be seen if those speed grades will gradually start to increase the ASPs back to $150 range. Because the reality of the situation is that Intel ASPs now are lower than they were a year ago, so the "price war" is more than just a perception.
Joe
Elmer,
You had a blank post on SI that got 3 recommendations!
It was his best post so far...
Joe
chipguy,
So in other words you admit you were being hypocritical and
disingenuous in even bringing up AMD unit sales earlier in
this thread. Thanks for clearing that up.
No, I posted information that RGood was apparently missing.
Joe
wbmw,
AMD showed a booted Windows 3 months after announced tapeout, and one would have thought that by then, they would be able to show a bit more than just the Task Manager screen. ANYTHING would have been better. At most, they demonstrated that Barcelona silicon in December was capable of at least running some simple scripts on all threads for a duration of ~3 seconds. At most, it suggests a Q3 launch is possible. In light of Intel's progress on their 45nm design, would this really get you excited?
Are you under the impression I am excided? I posted here very recently that I thought Barcelona schedule looked very tight.
Joe
chipguy,
The problem isn't that AMD grabbed 20+% of the x86 MPU
market in Q4. The problem is it grabbed a lot less at the high
ASP end and a lot more at the factory floor sweepings end.
You'll understand the implications of this a lot more in five
days.
I understood the implication of falling ASPs in March or April 2006, when I sold my AMD shares.
Joe
RGood,
That "Choice" is exactly what is killing Dell. Their choosing not to buy Dell and to be more specific folks ar not choosing AMD.
Just to update your info on "choosing" AMD.
About 4 to 5 years ago, AMD unit sales dipped to about 4.5M units. This quarter, the unit sales will be in 16 to 18M range.
Joe
Klaus,
I guess it depends how ambitious you want to get. Maybe the later time to market implies a more ambitious design, rather than just integrating existing design on the same die. We will see...
Joe
chipguy,
Freudian slip of the first order when talking about K8L. :-P
Either that or Fusion...
Joe
wbmw,
Booting Windows is the first step in the validation process, and easily the easiest thing to get working on first silicon.
Well, it is easy to perform test, but not exactly a peace of cake to pass. Booting Windows is a series of diverse code sequences. Passing it (= booting) means that the processor is roughly OK, and can proceed to more in debt test.
BTW, if it was as easy as you imply it is, why would the CPU makers trumpet the fact that their processor booted Windoes. The very fact that both Intel and AMD announced that their processor booted Window means that both companies consider it to be an accomplishment.
Joe
Paul,
Gee, I thought the ATI acquisition was not only about chipsets and IP necessary for modern graphics card, but also about time to market. Time to market absolutely sucks if it indeed is end of 2009.
It may be the most elegant solution, but every quarter that passes without some kind of "Fusion", less benefit AMD will derive from the $5.4B acquisition.
Joe
chipguy,
Got that backwards Joe. Most of the jobs at Dell depend on
access to Intel processors.
And Dell has finally learned the wisdom of reducing this dependency...
Joe
chipguy,
Dell is the big loser now in
terms of leverage against Intel in negotiations for pricing
and allocation.
Really? Some 20,000 Intel employees owe their jobs to this loser...
Joe
sh,
That's quite a reversal for HP and Dell - looking at worldwide figures...
Joe
wbmw,
In addition to having that information, I could get a better purchase price. Q2 is usually a bad Q, and usually, summer is bad for tech stocks in general.
Joe
Spaarky,
Ha. Remember all those threads about how stupid Dell was for not carrying AMD? How once they adopted AMD, both Dell and AMD would soar?
I love irony.
If you love irony, you will love to learn that the penetration of AMD processors in HP product line is much greater than in Dell product line. Dell barely started selling AMD processor based products.
Joe
Saturn,
Traditionally the CPU generates a bitmap for display, which is transferred from CPU L2 cache to the main memory, and also to the cache on the graphics chip. Having the graphics chip sharing the same L2 cache eliminates the time consuming transfers to the graphics chip.
I don't think it's done that way any more.
Joe
justaview,
AMD put the fear of God into Intel and now Intel is determined to return the favor.
I agree with that. I don't see AMD acting on it yet...
Joe
sparky,
60%+ GMs were the exception anyway.
60% GMs for Intel with current ASPs are a piece of cake for Intel in CPUs only. It gets more challenging with inclusion of chipsets and even more challenging with inclusion of flash and "other"
Joe