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Dear Chipguy:
Why do you use SPECbase instead of SPECpeak? Is it because Intel CPUs look better that way? Well for most CPUs we use SPECpeak. Using SPECint_peak, Opteron 148 beats Itanium2 1.5/6MB, 1477 to 1404. And that's with an older generation compiler, icc7.0. Given the boost using icc8.0 over icc7.0 given to same Xeons speeds and caches, Opteron 148 would get about 1750. Using the older compiler, AFX 53/940 would get over 1600. Using both, AFX 53/940 should get over 1900. When AFX 53/939 appears and with DDR500, that should be over 2000.
Itanium2 1.7/9 probably would get to 1580, far below even icc 7.0, AFX 53/940 or Opteron 150.
So your answer is that Opteron is faster than it tests and Itanium2 is slower than it tests. Itanium is very cache dependent. Opteron is not as the A64 512K vs A64 1M comparisons have found. 1/2 the cache hits A64 by less than 3% overall. It hits Itanium2 about 5.5% and a 1/4 cache hits about 18% in SPECint. SPECfp hits about 1.5% and 19% respectively (Evidently 3MB is almost enough for I2 in SPECfp).
Pete
Current K9 speculations have it adding additional FPmult and FPadd units to boost packed SSE2 performance doubling FPC (Flops per cycle) performance. Montecito may lose both SPECint and SPECfp.
Dear Chipguy:
No, it just shows how fast the 4 way Itanium systems will go the way of the Dodo. Customers will get more servers, more disk, runs their legacy software that they paid hard earned money for and still get even, stable and smooth reponse to their queries. A 258 second response to a simple transaction is quite unjustified. What did the Itanium do, go to the bathroom?
Pete
Dear Yourbankruptcy:
If you really look at the Opteron price declines, they are just moving up a bin. You can now get an 248 for the old price of a 246 and so forth.
Pete
Dear Wbmw:
Actually there are many dual Opteron server MBs that use 2 HT links to get higher IO BW. 1 link goes to AGP/PCI and the like. The other goes to 2 PCI64/66 buses each with 2 or 3 slots. That has a combined BW of 1056MB/s + 133MB/s + 2 * 533MB/s = 2245MB/s. When PCI express comes, that will switch to 1 link to PCI Express x16/PCI/SB and the other to dual PCI Express x16. Then the total BW would get to 12.8GB/s now and 22.4GB/s later (10 times of that now). 4 way Opteron MBs can still have 2 HT links with a diagonal or 4 HT links as a ring. The latter makes more sense from a expansion and IO bound tasks standpoint.
Since HT is a P2P link, HT tunnels for graphics may evolve to a 3 way HT switch, one link to the CPU, Graphics and SB. The other would be the HT to 2 PCI Express version.
Pete
Dear Wbmw:
The 2.4GHz Opteron system costs only $76K for the CPUs, memory, included internal HD, CDROM and case. The same for the higher Itanium entry is $252K. HP even added $76K more of disk to the Opteron system and still came out ahead in total cost. I think that the Opteron would have had a higher score, if it had the same smaller, but quicker disk. Certainly its tpc/$ score would be even lower. The Itanium using the same type of OS (server 2003 64 bit vs 32 bit for Opteron) and DBMS was slower.
Pete
Dear Joe:
Another thing about the two sets of scores is that the Opteron systems had much lower maximium response times and more than twice the disks than the Itanium system at the top. For one entry, deferred ship, Itanium had over 4 minutes (258+ seconds) for the maximum response and the Opteron in the same category had only 0.50 seconds! And a maximum response of any kind of 5.13 seconds, over 50 times faster than the Itanium. I guess those maximum resonse times required something that didn't fit into those large 6MB L3 caches, but the Opterons didn't break a sweat with their 1MB L2s.
Pete
Dear Wbmw:
You ever hear of a series regulator? It takes a supply voltage and produces a lower output voltage. Most probably this is an internal switching regulator or charge pump. They are easy to add to a die to get different voltages than those supplied. Of course AMD could use the lower VTT voltage of 1.25V to supply the cache memory. Of course VDDIO of 2.5V is a standard DRAM supply voltage and I haven't heard of any AMD64 CPU burn up supplying that to its attached DRAM. I guess Intel must blow all its Baniases with the 1.8V to its PLL supply as 1.484V is the maximum for the core supply.
I think you are grasping at fog and it keeps slipping through your grasp.
Pete
Dear Wbmw:
Oh so when AMD specifies something and it disproves some fallacy on your part, you think it can't be true? AMD states that S3 mode (called suspend in the MA64 datasheet) uses only 160mw. And then you turn around and believe Intel's TDP numbers with less basis as must be true no matter what. Even Intel admits that these TDPs are not worst case and so states that fact in those pesky notes.
If you or an OEM finds a part under those pesky conditions in the notes, that exceeds the specified power, they can return it as being out of spec. Face it, VDD is 50mv per the notes. VDDIO is 2.5V per the datasheet and VTT is 1.25V. Either could easily power the cache and VDDIO also powers the DRAM clocks to maintain a slow refresh. Banias does not have a DRAM interface.
Pete
Dear Wbmw:
Read the Athlon 64 Datasheet. VTT is powered first. VDDIO is powered next. Both are powered in S3 mode which is equivalent to Intel deeper sleep mode. But note 3 in even 30430.pdf states that VDD is +50mv nominal for the 160mw S3 state.
So you refuse to read the conditions by which measurements are made. Be assured, I do read those conditions. I guess you do not like that all MA64 consume less than 160mw during S3 and all Banias consume less than 1.35W. Well the truth hurts doesn't it?
Pete
Dear Wbmw:
You forget that the MA64 has more than one voltage input. VDDIO is powered during S3 and at 2.5V is more than adaquate to maintain cache contents. Evidently you can't read the MA64 datasheet. The 30430.pdf only contains the voltages that change within each bin. VDDIO is the same for all and is buried in that Pio level stated. I assure you that 2.5V is more than sufficient to power SRAM cache. Heck even Intel needs only 0.748V for that.
Did you even look at the MA64 datasheet? You could have even used the Athlon 64 datasheet, 24659.pdf, to see what voltages are present.
Pete
Dear Wbmw:
Have you forgotten how to read datasheets?
Min P state for MA64 2700 in stop grant mode is 2.5A at the Vcc of 0.90V plus 2.2W for Pio. That is 4.45W maximum. Yet doing the same for Banias 1.7GHz, you get 3.3A at 0.956Vcc plus 2.5A at 1.8Vpll plus 0.12A at 1.05Vterm for a total of 7.78W. I fail to see how the MA64 is higher given that the Banias uses 3.33W more. Banias sleep uses 3.3A at 0.956Vcc plus the 4.5W for PLL and 0.126W for Pterm which still uses 7.78W. MA64 2700+ uses only 2.4A at 0.90Vcc plus Pio of 1.2W for 3.36W. Banias uses even more power of 4.42W. Deeper sleep uses just 160mw for MA64 and 1.8V * 0.748Vcc or 1.35W for Banias. Banias uses 1.19W more.
Sorry, Banias just uses more power in these lower power modes than MA64. Live with it. And when given the same graphics hardware, Banias is quite slower especially in games.
Pete
Dear Wbmw:
If you carefully look at the conditions of Intel's deeper sleep mode, you will find that the core drops to about 0.75V and the current is 1.8A. For the MA64, the Clock is off, Vcc is 0, HT links are set to float and the DRAM bus is also floating, but the DRAM clocks are still on in a very low frequency using a 512 divisor with the caches being just maintained. During this mode, only 160mW are used. I believe that for Banias, Intel turns off the AGTL+ termination power, floats the FSB lines and simply maintains the cache contents.
As you can see, the is no core voltage so all you have is IO and cache memory power. Please read the conditions of state S3 and deeper sleep before making yourself make silly mistakes.
Pete
Dear Wbmw:
You must have an older version. Mine is dated April 2004, version 3.17. Go to http://www.amd.com and download the updated copy.
Pete
PS the new one adds many new flavors including FX53.
Dear Wbmw:
Unfortunately for you, most MA64 systems far outrun Banias based systems when all else are equal. Also considering that MA64 3400+ bins a whole lot higher than Banias 1.7GHz, your statement that Banias is superior leaves a lot to be desired. Even if you do not take into account that AMD's TDP have much more margin in them than Banias TDPs, the specifications show that in the power savings modes, Banias uses more power. 1.34W is over eight times that of 160mw. I strongly suspect that given typical temperatires found by the various sites, that A64 TDPs are much lower than that specified and that Banias ones are much closer to the given specification and possibly exceeds them.
That is the big assumption everyone makes that many do not seem to want to acknowledge. That comparing specifications only works if the margins are roughly equal. And it is clear that they are not.
Pete
Dear Wbmw:
Check page 20 of 21 in 30430.pdf. The specs for MA64 2700+ are there. Vcc*Icc+Pio=TDPmax for all AMD power levels. 2.5A*0.90+2.2=4.45W Sleep. Do not forget to add 1.05V*0.12A=0.126W for AGTL+ termination power and 1.8V*2.5A=4.5W PLL power for Banias. Only in deeper sleep are these off IIRC. Those 4.63W affect these supposedly low Banias power levels. All deeper sleep Banias are like MA64 S3 power state at 0.16W.
As to leakage, just look at the deeper sleep power levels, 1.3W vs 0.16W is a huge difference (and DRAM clocks for refresh are still active for MA64). Perhaps those smaller Intel SRAM cells leak more than the bigger AMD ones.
Pete
Dear Wbmw:
Look at the way AMD specified the CPUs for TDPmax. They take the absolute worst case for Iccmax*Vccmax+Pht+Pio+Pdram. This is specified at most 35W. Banias 1.5-1.7GHz has a TDPmax of 33.8W (I included AGTL+ termination and PLL power). Their TDP is some typical power no where near TDPmax for them. Now stop grant power for MA64 2700+ is at most 4.5W at min Pstate frequency and 15.4W at max Pstate although with C&Q, I do not conceive of a time when this occurs since I think that first the freq goes to min, the Vcc to min and then the CPU is halted. For Banias 1.5-1.7 this is 17.3W. Sleep mode is 3.4W for 2700+ (5W for all MA64) and 17.0W for 1.5-1.7. Deeper sleep is 0.16W for all MA64s and 1.35W for all Banias. Since AMD's numbers include all external sources and the DRAM bus, Banias should include power sourced into the FSB and the DRAM bus(es) on the NB.
Still it is apparent that Banias 1.5-1.7 uses more power at all points than MA64 2700+ especially the low power points. And it shows that the 130nm SOI peocess (or A64 design) leaks less than Intel's 130nm bulk process.
Pete
Dear Wbmw:
From previous posts, Banias is not lower power than MA64 in any mode lower than full speed. In stop grant mode, sleep or deeper sleep, Banias actually uses more power than MA64. Banias 1.7G and MA64 2700+ match well in stated maximum power mode when not counting the NB used by Banias (using TDPmax as used by AMD). The performance of the 2700+ is a cut above the 1.7GHz. If pushed into 64 bit mode and/or larger memory, the 2700+ is significantly faster.
Pete
Dear Chipguy:
Where 13K systems were 2P, that still does not mean that 6K systems had many times more CPUs. Many of those systems were 1 or 4 way. 300 SGL Altix systems may have some that were above 32 way max, but that does not mean all were. Does that mean a single HP LC3000 server made up of 32 compute nodes and a control node counts as 1 server or 33? Or a 8 node x325 cluster count as 1 server or 8 (or perhaps its double counted)? Then 1 Opteron server could have over 512 CPUs. Red Storm might count as 1 server, but have 10K (or is it 30K now) CPUs. And how do you count 2 Itaniums in a 8 way box?
You are still assuming that Itaniums are shipped by OEMs as soon as they get there. But how long do they "burn in" the CPUs (typically a few days to get rid of early portion of the bathtub reliability curve), how long do they test (about 1 week especially those large multiway systems), how long between shipments (1 or 2 weeks) and how long do those systems sit on the shelf (2 to 4 weeks)? Intel may book the sale when the CPUs arrive on the loading dock, but the OEM (heard of AR?) may pay when the systems are shipped to the customer.
Since there is a lag of 8 to 13 weeks between Intel saying they are shipping a CPU (to OEMs) and the OEMs shipping it to customers (when IDC picks it up). If 13K systems shipped in Q1, then 30K systems shipped with 100K CPUs (3.3 each). Similarly 150K Opterons may have shipped in 75K systems (2 each) from Q2/03 to Q1/04, but 180K CPUs shipped in Q1 for 80K systems in Q2 (2.25 each since 4/8 ways are now selling). AMD seems to wait till an OEM builds a system or a retailer sells a CPU before it is booked.
Unfortunatly many (including myself) fall victim to this and other lags. The major ones people fall victim to are the 13 week lag from start wafer to CPUs arriving at OEMs and disties, the 13 week lag between demand surge and supplies surging, the 12 month lag between FAB equipping and production start and the 12 month lag between CPU design tapeout and production start. So you are not alone.
Why don't we wait for the may IDC report on Q1? We can argue then with better numbers.
Pete
Dear Chipguy:
Apology tendered.
Although this still doesn't directly make it to CPU sales. The article shows that 2 CPUs per Itanium server was the norm. Thus, Intel may have shipped 100K Itaniums to OEMs, that does not mean that the systems shipped had 100K CPUs in them. At the 2 per system level cited, only 38K IA64 CPUs shipped. Also the numbers for Opterons cited, shows that 10.7K Opteron servers shipped, almost all 2P servers. That puts 20K Opterons in Q3 so a projection shows 10K Opterons in Q2, and 40K in Q4 (35K servers * 2 CPUs each = 70K. 150K by Q1/04 makes 80K in Q1 more than 30K Itaniums (12K servers) in Q1. But we should wait for Q1 IDC sometime around mid May.
Also sales of Itanium servers was $490 million while $190 million for 35K Opteron servers in 2003. Projecting that to Q1 this year shows that Opteron probably got $220 million while Itanium was at $300 million in server sales. Projecting it to Q2 gets us to $440 million of Opteron servers and $500 million of Itaniums assuming no decline due to iAMD64/AMD64. Adding in A64 FX systems which are Opteron 148s and 150s, that rises to $280 million and $560 million respectively. Of course broadly adding in all AMD64 systems, (430K * $1500 each) we get to $925 million in Q1 and (860K * $1300 each) to $1.68 billion.
Pete
Dear Greg:
Where is the tier 1 8 way Opteron server? No tier one has although Sun is working on one. Microway and Racksaver made Opteron clusters for a year but, IBM and HP only came out with theirs less than 1 quarter ago. As for Itanium, SGI is not tier one yet it is frequently cited. HP is a special case like IBM with Power, those are chips they developed so they can not be used as examples. Even then IBM had a MPU that could have replaced their mainframes in the 70's, yet chose not to to keep high margins. Just like DEC VAX and its MicroVAX MPU. Like tier 2/3 OEMs were using MicroVaxes in servers before DEC used them. Tandem was not a tier one when they came out with fault tolerant mainframes. They became a tier one because of that. Like Compaq did making 386 servers. Time and time again, innovations were made by tier 2/3s (they could later become tier 1s) long before tier 1s.
So history has shown that more MPUs were made into servers by tier 2/3s before tier 1s. HP was not a tier one server maker when MPUs came on the scene. Nor was Intel. Dell didn't exist. DEC was not tier one when they made the first minis. Sun was not tier one when they designed SPARC. IBM was a tier 1 server maker, yet they did not make the first x86 server, 286 server, 386 server, 486 server, Pentium server or any subsequent x86 server. None of the Tier 1s did at that time. No tier ones used DEC, HP, Sun, MIPS, Motorola when those came out.
History sides with the tier 2/3s.
Pete
Dear Chipguy:
What? You do not give links as proof! My reading shows that as YoY growth! Just like this server report from IDC: http://www.in-sourced.com/article/articleview/1388/1/1/ But, until you show public link to you numbers, I simply think you missed that it is YoY growth like the 22% cited in this article is for YoY growth, but those who quickly read it may assume that the growth is 22% QoQ. They are wrong! Just like you apparently are.
So if you want to refute me, post the link to the relevant document. "I have it on this private document" does not make a usable proof. Even a link from a news item refering to that document quoting the numbers is better than "Its from a secret propriety note flinched from the garbage so I can't give you a link". Else, you have no proof.
Pete
Dear Greg:
There is a 2nd/3rd tier OEM making 8 way Opteron servers. Which tier one is building one? Crucial does make a 4GB PC2100 and a 2GB PC3200 DIMM. But 2nd/3rd tier DRAM OEMs make PC4400 DIMMs. So far no tier 1 DRAM OEM makes one. This may change in the future, but so far most cutting edge Opteron systems are made by tier 2/3 OEMs. Microway/Racksaver made HPC Opteron clusters long before HP, IBM or Sun did. I think it is you who should prove that tier 1 are less conservative than tier 2/3. History proves otherwise.
Pete
Dear Chipguy:
The numbers you cite are for YoY growth, not QoQ growth, which is typical of IDC's style in their reports. So your numbers are as much garbage as your assumptions. There is no knowing how many absolute systems they mean since they do not seem to break it out by CPU unit sales and neither does Intel. 27K*1.80 = 47K not too far from my 42K estimate for Q2. And I think that Intel's adoption of AMD64 will put a crimp on future IPF sales. Since you can get 8 way Opteron servers right now and soon will see 16 way and 32 way ones not mentioning the huge N-way supercomputers (N>10k).
Pete
Chipguy:
Given that the ramp is probably exponential in the initial stages, it is more likely that the sales for Q2, Q3, Q4 of 2003 and Q1 of 2004 were 10K, 20K, 40K and 80K respectively. Now IPF sales were likely to be 22K, 27K, 32K and 37K respectively for a total of 118K which is less than Opteron. Projecting Q2 sales, I get 160K Opteron and 42K IPF. Which makes it likely that Opteron revenue will be greater than IPF revenue this Q. In addition, A64 FX (equal to Opteron 148) sales should also be included as workstations/high end PCs like Xeons are handled. That would add about another 70K up to Q1 and probably make Q1 the quarter where Opteron revenue crossed IPF and pushing this Q to twice that of IPF.
Furthermore, since AMD64 is a 64 bit CPU, all AMD64 shipments can be argued as 64 bit servers, workstations and mobiles. About 850K shipped through Q1, more than 7 times IPFs modest numbers. And AMD64 has far more revenue to Q1 than IPF has to date. Makes the readers wonder why you and other Intel apologists continue to shrink the IPF target market to tiny niches for comparisons.
Pete
Dear Dan3:
Mobile Athlon 64 2700+ (1.6GHz) has a peak power of 35W which is an upper bound meaning that the worst MA64 2700+ will not ever exceed this value. The same upper bound for a 1.5-1.7GHz Banias, Pentium M, is 34.5W. Sleep mode for a 1.4-1.7GHz Banias uses a maximum of 12.8W compared to any MA64 of 2.2W. Deeper sleep for any Banias is 1.42W and for any MA64 is 0.16W. So in all sleep and stop grant modes, Banias actually uses more power than MA64. And this doesn't include the memory portion of the Intel NB. This is according to the latest datasheets 25261203.pdf (Intel Pentium M) and 40430.pdf (AMD64).
Given these specs, it looks like Banias is the higher power using CPU. Only the LV (up to 1.3GHz) and ULV (up to 1.1GHz) version have lower power usage, but are slower than any MA64.
Pete
Dear Alan:
Do you remeber that Athlon 64 3000+ was selling from Pricewatch before AMD announced it? How about the Athlon 64 2800+? How about HP and the socket 754 AXP? They had it on their web site for over a week before AMD acknowledged it.
OTOH, Intel announced the 3.4 P4 EE long before anyone could buy it. Currently it is missing from even Dell and HP. Ditto the 3.4 and 3.2 P4E. When your best customers can't get them, something is really wrong! They have not had leading edge product available when announced over the last year. 3.4 P4 EE was announced in 2003, it still doesn't seem to be in production some 4 months later.
Pete
Sgolds, IBM makes less money making nVidia GPUs per unit area than they would A64s. A64 FX and Opteron are the same exact chip. There is no real difference between Opteron 1xx and A64 FX. Also IBM does fab NV40s and nVidia sells them, not IBM. So if AMD contracted IBM for 1 million A64 90nm Winchesters at $75 each per known good die (minimum speed at XGHz) and it costs IBM $30 each to make them, IBM would be very happy getting $45 each. AMD would also be happy because they get 1 million $120 ASP A64s and make $45 each. It would not take a lot of volume for IBM to make a large net profit. Especially where the fab utilization is below the break even point as it is now. 2.5 million per Q A64s probably would put IBM Micro in the black. It uses less capacity than the 4 million per Q NV40s that IBM Micro fabs now to do the same. Heck given that NV40 is over 300mm2, they could make 12.5 million A64s for the same wafers and A64 would add 5 times to the bottom line.
And it would not be in AMD's best interest for IBM to fab Opterons for internal use as it gives too much control away for little gain. Besides, IBM Micro to AMD to IBM server or IBM PC keeps the incentives to do well what each is best at. Otherwise IBM Micro would be treated by IBM server like Intel IAG treats Intel Other (you're there to make me look good, all successes are mine and any disasters are yours).
Pete
Sgolds, one of your assumptions is faulty.
Re: "Intel can flood the market and still keep higher ASPs than AMD because of their reputation and their dominance of the manufacturing game. In other words, AMD just can not manufacture enough processors, and in a world with shortages of AMD product then Intel can demand a higher price as the only game in town. Companies will pay it because they still get a price premium for Intel computers, and all the other component costs are the same between the two platform architectures."
This is only true if Intel has comparable or better products. If Intel is behind, AMD could sell all they make and then Intel will sell the rest. Intel's ASPs would drop without causing as big a drop in AMD's. Suppose that Intel cut every price in half. Intel loses $3 billion in revenue, but no costs. About 5 million of AMDs higher end product has 90% ASPs and the low 2 million gets cut in half. AMD loses just $110 million in revenue. Intel has a $500 million dollar loss and AMD has $50 million. AMD could make up half of it from flash, Intel couldn't even get back 5% of theirs. Intel's stock price would drop into its book value or about $5 a share, AMD's may drop to $12. Next quarter, AMD moves completely to AMD64 and returns to profitability, Intel loses another $500 million in revenue and has $1 billion in losses.
Thus Intel loses big time and management would be replaced ASAP. In their own self interest, Intel would not do this. They prefer to stab AMD in the back using incentives. It takes a far smaller hit to do it, but that requires return to comparable products.
AMD also has the option of having IBM's foundry make AMD64 low end CPUs efectively doubling output to 40 to 50% of the market. Market is about 43 million CPUs a quarter. 20 million 90nm Winchesters would get $150 ASPs for $3 billion forcing Intel to $3.5 billion from $6 billion in Q1. So AMD at 90nm with IBM foundry could drop Intel to just making money, if Intel has not gotten comparable performance by 2005. End of 2005, AMD will ramp 65nm and could make the entire market sometime in 2006 with IBM's help. With a remake of Fab 30 in 2006, they could do it alone by 2007. However, I suspect that they will build another fab for 300mm 45nm starting in 2005 for 2007 production.
Pete
Dear Bob:
I did heavy duty Oracle administration. From the posts so far it appears that both your log files and the global area is not large enough for your database (just think that deleting 300K lines by 40 bytes adds 12MB to your journal each time where each transaction has to fit into the redo area (1MB)). Typical rule of thumb has always been that for a 40GB data set you need about 4GB of memory (10%) of which 40MB in the redo area, 1GB in the variable area and 1GB of database buffers. These type of errors can also occur if the data base is full. Another criteria is to keep the database area to be twice the size of the stored data (tables and indicies).
So the first thing is to backup the files. The fastest way to backup the files is to shutdown the system, mount a hard drive with enough space to hold all the files, boot the system and copy data from the current files to the new hard drive. Alternatively if you are using some logical volume management system is to extend the DB filesystem by adding additional physical areas to the logical group and proceed as above. This should copy at over 20-30MB/s using either method so should take no more than 30 minutes.
By the way, by using hot swap type IDE or SCSI trays (HD in a hot pluggable tray), this can be used as a method of taking fast snapshots of the database and then can be swapped with another drive tray and moved to a box that simply has a small HD, the hot swap tray and a tape/DVD-R backup unit to back up the data. Another more elaborate setup is to 3 way mirror (RAID 1) the database, then detach the 3rd way to backup from and then reattach to resync the 3rd mirror. This can be done without stopping the database at any time.
The next thing is to increase the size of your global area. The third is to add additional log files and/or make each bigger. You then should be able to mount/restore the database.
Pete