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eventually, O'Melveny and Myers will know this, also.
Somehow I think that firm probably has a better understanding of antitrust law than you do. Call me crazy, but that's what I'm guessing.
Is that your 'type'?
I'm afraid it takes something other than 'logic' to get you from my definitive counterexample to Paul's ridiculous thesis to 'AMD can fire their engineering staff and hire lawyers instead'.
Yeah, good point there, Paul. I mean look at 2005. Suddenly, in June, AMD started "beating the lawsuit PR drums", and look at what happened to their earnings in Q3 and Q4... oh, wait...
I think those parts may have the SiGe worked in, if they are really 3.0 to 3.1GHz on air cooling at standard voltage. SiGe is being added to 90nm, in addition to 65nm. Although week 50 would be early for a Fab36 part-- maybe they'll incorporate SiGe into Fab30 as well?
What makes you think AMD won't release a 3.0GHz FX if they need to?
Don't forget the improved SiGe strain that will be incorporated into the 90nm process.
Because it is to align with the bare minimum FBD availability for launch. A compromise between Intel (worried about PR) and the OEMs.
BTW, I'm afraid your "Dempsey will beat Opteron in 2-socket systems" (in Q2) ain't gonna work out. Once again, you fall into the trap of comparing Dempsey against what AMD had 6 months ago, instead of what they'll have in Q2.
Does DDR2-800 / 1400MHz HT / 2.8GHz DC help jog your memory?
And you'd better pray that no virtualization benchmarks are run. Dempsey will be slaughtered.
BTW, what is it with Intel and immature memory technology?
They keep shooting themselves in the foot.
http://www.theinquirer.net/?article=29576
The problem lies with memory, or lack thereof. FB-DIMMs are running late and hot, but they work well when you can get enough. That is the problem, they can't get enough to launch at a level that Dell et al would find acceptable.
I beg to differ with Charlie on the blame aspect-- Intel chose FB-DIMM tech for the Dempsey chipset, and now they pay for it. How many quarters of "constrained" FB-DIMM availability will Intel be facing *after* they launch in May?
Uh huh. And how about 2 1Us in a rack, each containing 2 sockets?
It's funny. All Intel has to sell is Poxville, and they've already demoed Dempsey, and now are making all sorts of noise about Woodcrest, and now feel the need to be first to publicly demo a QC part they won't launch until 2007.
Smells like desperation. I guess they aren't expecting much from Dempsey?
Yes, but until now I haven't made an official sell recommendation for AMD, nor an official buy recommendation for INTC.
I understand. We should ignore all your predictions and claims until and unless you announce that they are "official".
Will you be getting those posts notarized, as well?
Or maybe you'll add a footer to those posts you want us to take seriously?
Something like:
*** This represents an OFFICIAL post from wbmw, and actually DOES represent his beliefs on this matter.
You can't break your 2-socket motherboard in half and use one piece of it either.
No, why would they? Another MCM solution Intel won't launch until Q107, with dreadful performance, while AMD has demoed QC privately since October, and could launch in Q3 if need be.
Yeah I just did that... to the lifeboats! She's headed to the bottom!
and just recently Sun launched its Get off the 'Itanic'...
LOL!!!
Actually, the MCM (vs. single die) has some negative performance implications. They may be small, but they are there. And if it is for PR purposes ("We had the first dual core!"), well, why not count a 2-socket system? Isn't that good enough, as far as the software is concerned?
Rink, below the text from Digitimes (below), there is a table which indicates Yonah with Napa, and Merom with Santa Rosa. I'd have thought they'd indicate "Yonah/Merom" with Napa, were that possible.
Given that Merom has higher power requirements than Yonah, it seems like it won't drop into existing Napa notebooks very easily, even if the socket supports it.
If Merom is also pushed out to March, that should give AMD *three* full Q's of 64b DC notebook lead.
Intel’s new notebook platform Santa Rosa to come in March 2007, expected to boost notebook shipments
Monica Chen and David Tzeng, Taipei; Steve Shen, DigiTimes.com [Wednesday 8 February 2006]
Intel is expected to launch its new notebook platform, Santa Rosa, in March of next year and the new platform could help boost global notebook shipments pass 100-million units in 2007, according to sources at Taiwan notebook makers.
Santa Rosa will be based on Intel’s forthcoming new dual-core notebook processor Merom which boasts 64-bit computing capability, said the sources, noting that the new platform will also feature enhanced wireless connectivity.
Intel and Taiwan notebook makers had originally targeted to roll out Santa Rosa-based notebook by the end of 2006, but have recently re-scheduled the launch date to March 2007, the sources noted, adding that the new schedule allows Taiwan makers more time to develop notebooks based on the new platform, while extending sales cycle for the recently launched Napa-based notebooks.
Taiwan makers estimate that global notebook shipments will reach 82-85 million units in 2006, up from an estimate of 65 million units for 2005, the sources said. With the planned launch of Microsoft’s Vista OS in the fourth quarter of 2006 combined with Santa Rosa in the first quarter of 2007, Taiwan notebook makers believe that global notebook shipments will exceed 100-million units in 2007
Hmm, they're wrong about Dempsey being true dual core. It's another MCM, per Intel's previous info. Yonah was the first true dual core for Intel.
Others have reported Dempsey slipping into Q2 (a few weeks back?), but May is the most specific I've heard.
2 reports today... Dempsey delayed until May, and a claim that Merom is delayed until 2007 (!).
Dempsey delay (and Paxville rebates) suggest AMD will gain significant server share in Q1, and now Q2 looks locked up too.
I suppose if Merom were going to be Sept/Oct, that gets to close to the cutoff for the holiday build, so it gets pushed into Q107 so it won't Osbourne Yonah Xmas sales.
If true, AMD gets two full quarters of DC 64b mobile exclusivity.
You already predicted INTC stock would outperform AMD stock in 2006 at the beginning of this year. I told you it would be the other way. What's the matter, you need another chance already?
I guess Mossesman and I share something similar in our outlook for AMD.
Yes, extreme bias.
I am growing more bearish by the day.
That means AMD prospects are growing more bullish by the day.
and just about everything is priced into the stock,
It is? Wall Street is confident they'll earn $2/sh in 2006? Really?
even a design win from Dell, no less.
No. A Dell announcement will be good for +$10 within a week of announcement.
Will AMD blow past Q1 forecasts?
Probably. They did in Q3 and Q4.
And what's left after that?
Continued increases in capacity, gains in market share, and gains in earnings should do nicely.
If there was ever a good time for someone to update their investments, it would be right now.
Says you. And like Hans, your investment advice has been TERRIBLE so far.
I think Mosesmann is so ridiculous that it is pointless to attempt to analyze his 'reports'. I'm surprised he hasn't been fired by now, considering what he may have cost AMD and INTC investors who listened to his advice.
As far as you also being a contrarian indicator, I was referring to your advice to others to sell their AMD stock when it was in the low $20s, and your sale of AMD stock in the high teens about 8 months prior to it passing through $40.
http://www.siliconinvestor.com/readreplies.aspx?msgid=21004524&nonstock=False&subjectid=3613...
Mosesmann, calling 1 year ago for a 12-month target price of $10/sh on AMD. Oops, he was wrong by a factor of FOUR.
Also, you have Elmer "flash is profitable" Phud making an embarrassing claim.
It would be quicker to list the parts he agrees with, I'm sure. Hans doesn't exactly have a sterling track record with his AMD / INTC advice. He's almost a perfect contrarian indicator, speaking of which... :)
Keith, my thoughts here: http://www.siliconinvestor.com/readmsg.aspx?msgid=22142908
----------------------------------------
HKEPC AMD Desktop roadmap.
http://www.hkepc.com/bbs/viewthread.php?tid=550178
For desktop, AM2 socket. These slides don't quite look like official AMD stuff, but if correct:
- June Computex launch of AM2 stuff.
- DDR2-667 (PC2-5300/5400) brings memory bandwidth up to 10.7GB/s.
- At launch: FX-62 (so not called FX-65?) 2.8GHz DC (125W TDP). Also 5200+ / 5000+ X2 parts @ 2.6GHz x 2 (89W TDP)
- HT freq remains at 1GHz (so overall HT BW = 2 bytes * 2 directions * 2 cores * 1GHz = 8 GB/s (same as current X2 parts)
- I assume this means HTT remains at 200, despite some comments under the linked post, and this is supported by the CPU speeds.
- uniprocessor systems don't really need more HT BW, so this makes sense. I assume the Socket 1207 parts will support 1400MHz cHT, based on rumors so far.
- total "CPU BW" therefore 10.7 + 8 = 18.7GB/s
- *desktop* 65nm in H107 (makes sense, I'd guess mobile & server first to 65nm in H206, like the 90nm transition).
- I think they are wrong in their speculation about higher speedgrades waiting for 65nm. People are again mixing up *family* TDP with part TDP. The 2.8GHz FX-62 is probably not using the full 125W, with the 5200+ down at 89W (And that's quite nice, currently, the 4800+ is at 110W. So +200Mhz, -21W TDP still at 90nm for the 4800 Rev E --> 5200 Rev F. DDR2 helps a bit here.)
Babelfish:
Newest AMD product road map FX62 estimate in June issued
Received the AMD newest product road map to renew, had disclosed in 2006 the AMD processor development road to, new generation of Socket the AM2 processor plan will be able in 2006 June to issue to Taiwan Computex, including double core Athlon64 x2/Athlon64 FX Windsor, single core Athlon64 Orleans and low step Sempron Manila, Windsor and the Orleans core will be able to increase supports AMD Virtualization Technology, and changed supports the DDR2 memory body type. Low step Sempron core Manila although certainly does not support AMD Virtualzation Technology, but in constructs the memory body controller will be able to promote to supports Dual Channel the DDR2 technology, when similarly will use the AM2 connection command to use the family will promote in the future Gao Chieh AMD product not to have needs to replace the main engine board. Has also disclosed them in the road map although issues Socket AM2 in the year, but old will have supports DDR memory body Socket 939 and Socket 754 can continue to supply goods the market until in 2007 Q1 up to, but 2,007 first half years AMD will be able to induct 65 ?? metric systems regulations, including the code number for double core Brisbane and single core Sparta, will retain uses Socket AM2.
While issued Socket AM2 will be able simultaneously most Gao Chieh AMD tabletop processor Athlon 64 FX-62, Windsor 90nm when the SOI system regulation double core processor the arteries will be 2.8GHz, 128KB L1 and 1MB L2 Cache, in will construct the DDR2 ????? memory body control, will support 16Bit 1GHz Hyper-Transport but the high frequenciest width by the former generation 14.4GB/s promotion to 18.7GB/s, will support AMD Virtualization, Cool'n Quiet, function and so on Enhanced Virus Protection, but the processor highest power loss has promoted to 125W, will contrast 2.6GHz double core /1MB L2 Cache Atholon 64 5200+ to have 89W to appear the straight line the rise, Looked like AMD appeared when 90 ?? Mi Ihsien on the arteries bottleneck, a higher speed processor only can wait for 07 years 65 ?? rice approaching, because in 06 years road map AMD has not certainly compared FX62 Gao Chieh the product.
Via iHub.
Your 'explanation' was ridiculous on its face.
You're exactly right. It's amazing to see the creative excuses thrown about for checking for 'Genuine Intel'. They remind me of Baghdad Bobisms.
The only unethical behavior I've seen is ...
You must have your eyes closed, then.
Intel tests for 'Genuine Intel' to prevent mislabeled 3rd party CPUs from vendors like Via or Rise from breaking the code.
Oh, please. Give us all a break.
*unless* it's an optimization that works equally well for AMD and Intel CPUs.
Wrong. Intel still tests for 'Genuine Intel' to prevent optimization for AMD parts in such cases.
Deliberate crippling detailed here:
http://www.swallowtail.org/naughty-intel.html
Is version 8 any better?
We've now upgraded to version 8.1 of the Intel Fortran Compiler as it now compiles our code more-or-less successfully. I was hardly surprised when I inspected the code for __intel_cpu_indicator_init: it's more complicated than it was in version 7 (checking for SSE3 support, among other things), and all of the math intrinsics have SSE3 equivalents added, but the checking for 'GenuineIntel' is still present. One difference is that Intel now openly admit that SSE3 functions are available only for Intel chips, but as far as I am aware it is not explicitly mentioned that code compiled with the -ax flags will not use any vectorisation on non-Intel processors and that SSE/SSE2 vectorisation is crippled on non-Intel processors.
[...]
The results for all unit tests of the software were identical between the original and patched versions. As can be seen, patching out the 'GenuineIntel' check makes no difference to the P4, but increases the performance of the Opteron by up to 10%. If the code was compiled with '-axW', then the Opteron really suffers: the 'Simplex' test is more than two times slower (it uses lots of exp() calls, and hence really benefits from vectorisation).
[...]
Conclusions
It is a shame that the Intel compiler, which use to be almost the no-brainer choice if your primary concern was fast code, is now being coerced into being a marketing tool. Crippling the output for non-Intel chips may mean that some published benchmarks may end up bogusly favouring Intel over AMD, but the cost is that if you want to release fast production code I can't recommend the (unpatched) compiler. There are an awful lot of AMD machines out there!
To Intel: there is a standard mechanism out there (invented by you!) for questioning a CPU as to its capabilities. You should be using that, not checking for the presence of your trademark. I don't expect Intel to support AMD-specific extensions, and I also don't expect Intel to have to test its compiler on AMD CPUs. However, if a CPU states that it can do SSE3 or whatever then I expect the code produced by the Intel compiler to use SSE3 instructions rather than to check first if the chip was made by Intel. It was not acceptable for Microsoft to go out and deliberately cripple Windows under DR-DOS, and likewise it isn't acceptable for you to cripple a product that you sell for not inconsequential sums of money so that it won't perform properly on competitors' hardware.
But really, given Intel's history of unethical, illegal behavior, who would've expected anything less of them?
Next you'll be telling us that the Intel compiler doesn't deliberately cripple code for the K8.
First off, there are hardly *any* 64-bit apps available under Windows, which makes the discussion of 32-bit application performance hugely relevant.
Yeah, that's just HUGELY relevant to a discussion of whether or not Intel's 64-bit implementation is lame or not-- see how it performs on 32-bit code.
whose newest revision was tuned and optimized
Does that mean "not deliberately broken for AMD processors by the Intel compiler", or did you have something else in mind?
You mean like this comment from your link: Perhaps most encouraging is the gain demonstrated by Cinebench. As we see more 64-bit applications emerge, memory hungry apps may indeed benefit from the larger address space. Once again, we see AMD with a larger gain (29%) when moving to 64-bit, versus Intel, which only gains a bit over 16%.
Are you sure you want to continue with the myth that Intel's 64-bit implementation is as good as AMD's?
I think you'll find that the "investment world" would view below the midpoint yet above the low end *rather* differently to below the low end.
Based on the Poxville / 8xx fire sale, I'd say they are heading for the lower third of their range.
How exactly did you get "underperform their Q1 guidance" from "low end of Q1 guidance"?
Sounds like you're having trouble understanding the concept here.
Exactly. :)
Sounds like Intel is headed for the low end of Q1 guidance.
You are grossly misinformed if you think that server applications are not multithreaded. Didn't you ever stop to wonder why folks buy servers with more than one socket?
It ain't just to run lots of different single-threaded apps at once.
You do realize that the application software doesn't care if the cores on are on one device, or spread around multiple sockets, right?
And why do you think AMD's DC parts gave them such a crushing advantage when Intel had none (or lame ones, a la Paxville), and drove their marketshare up nicely?
Hello?
Then again, I guess you're the guy who thought AMD would be at $17 last month, and now you're "calling" for a $20 drop.
Maybe these predictions were based on a complete misunderstanding of the nature of server applications?
Yep, AMD is boosting L3 cache for all Opterons @ 65nm, from the sound of it. 4MB L3 shared between cores.
Well for starters, there's no Intel 4-socket chipset until... H207? Later?
Then, you may want to read through this from end of Dec:
At the 2S 8C level, if there ends up being a race, AMD will crush Intel, something that will continue at the 4S 8C and get downright abusive at 4S 16C.
http://www.theinquirer.net/?article=28639
mas, you need to consider >=2-socket systems.
'Novelty' is reserved for the 'science fair' IPF parts. Surely you of all people should know this by now?
Alan, dual die Woodcrest will not be competitive. They'll choke on the FSB. And I'll guess you won't see them before Q207 at the earliest.