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The code on that system is not all recompiled for Intel. Some of it is using Rosetta which does some sort of binary-binary translation. I would expect much better results when the apps are recompiled with the 'fat binary' technique (where an executable contains code for both Intel and PowerPC).
Tukwila cancelled? Is this the IPF effort by the ex-Alpha team that Chipguy has been hyping here for the past few years?
http://www.theinquirer.net/?article=20286
If their slant on it is right it sounds like there will be some very upset ex-Alpha design engineers.
I think AMD knows this
Your assumption is correct: Dual core will not cost more from MS:
http://www.theinquirer.net/?article=19165
In other words, they never said it.
Waffling about their pricing policy doesn't change that.
There seem to be gaps in the logic where you prove that Intel have a lot of 2.4GHz chips in warehouses. They sold a lot of 2.4GHz chips in the past, therefore they have a lot of them left unsold?
"For years, Intel has emphasized clock speed, implying that a 3.6GHz CPU will best a 2.4Ghz CPU without fail."
Is this some sort of urban myth of the PC industry? Can anyone point to anywhere Intel actually said anything like this? I don't think so.
OK, so I'm out of touch:
What MHz do the 4000+ and the FX55 have?
The fact that they are shipping mobile first indicates to me that:
* The 90nm version has lower power
* Either (or both)
+ Quantities are pretty small
+ Bin splits are not that good
In which case it makes sense to get a good price for the chips by selling them as mobile chips rather than a poor price as desktop chips. Whether or not the bin splits are poor it is clear that they are not mind-blowing yet, or they would be selling them as FX5xs.
I think 90nm looks good, so I'm happy to keep my AMD shares.
When AMD say the dual core version has the same power as the single core did at 130nm that doesn't mean they have halved the power. Many parts of the chip are not doubled in the dual core version, particularly the bits that have to do with communication with the outside world.
I don't think it was quite double. The yearly average for crude peaked at around $73 (2004 prices) according to http://www.nyserda.org/constant2004prices.pdf
And remember, the early 1980s sucked.
Shares of HP took a nose dive this morning
"HP has been phasing out much of the old Compaq line and looking for customers to move onto its Itanium server systems. The Itanium server revenue, however, does not seem to be offsetting the Compaq losses."
http://www.theregister.co.uk/2004/08/12/hp_q3_execs_out/
8 CPUs in a 1U design? Sheesh!
Page 12 is a cracker:
* Volume production of 90nm AMD64 parts began Q2-03
* Revenue shipments of 90nm AMD64 parts planed to start in Q3-04
* 90nm SOI process provices significant power reduction
etc.
Interesting Dothan story at that site. Does Dothan use more power than Banias? Say it ain't so!
If they are going to move the Banias core up to desktop and server, obviously they will have to give it a new system interface.
Judging by this link they will have to teach it about PAE36/PAE40 too: http://article.gmane.org/gmane.comp.video.mplayer.user/28035
I think those two things are the least of their worries actually. It's the actual ALU/registers and instruction decoders that are more difficult to rush.
Like Bob Colwell said, CPUs optimised for multiple threads are what you do when you've run out of good ideas for improving single thread performance:
"The way I view it is, when you get to this point in the maturation of the industry, and you've played this game so many times that you don't see any obvious wins sitting out the front you start looking at the sides, and you say are there any other games I haven't played over there? Multithreading is one of those. That idea has gotten kicked around as early as the 80s, with respect to CPUs. It wasn't worth doing until we sort of said 'it's really kind of cheap, and there's nothing really compelling down the mainstream, so we might as well play that game'."
About 73 minutes into the talk.
I guess it's best not to get ahead of myself here. Tejas was going to be the successor to Prescott, so it will be a while before its absence will be felt. It looked rather incremental to me: Same process, same basic architecture a few new multimedia instructions a larger cache etc.
I guess the significant thing here is what it says about the whole Netburst line. In theory it was supposed to be just getting into its stride at 90nm, in fact it seems to have hit a brick wall.
That's the 640 million dollar question! EOM
So dual core Dothan instead of Tejas?
It's going to be very interesting to see how high a clock-speed optimised version of Dothan can clock.
No rumours at all about 64 bits or NX in Dothan so that will be a marketing 'challenge' .
> Xeon is a bottom feeder
And an excellent bottom feeder it is. If Opteron feeds only half as well from the bottom then I'll be a happy stockholder.
Edges out the PGI compiler: http://www.spec.org/cpu2000/results/res2003q4/cpu2000-20031117-02630.html
In fact it's the best SPECfp (base and peak) for an x86 chip.
If you don't count Itanium II as an x86 chip.
And OK, the Opteron is not actually in x86 bit mode for most of the results shown.
On the int side they get beaten by Intel's free 32 bit compiler though. http://www.spec.org/cpu2000/results/res2003q4/cpu2000-20031117-02626.html
It means AMD aren't confined to the sub-$25000 niche you were talking about a few weeks ago.
That's a terribly slow ramp for Hammer if true.
"what I hear from consumers is that anyone who buys a system from any vendor ends up complaining about the quality of tech support. I don't think there is such a thing as 100 percent excellence in this area, with one exception, and that is eMachines."
Interesting. Are eMachines the new DELL?
I think it's been done.
At least in the toons
http://www.snpp.com/episodes/mini/MC25.html
Oh dear. I presume it isn't growing very fast if they think they can wait a few weeks before operating?
Good luck with it. You're "lucky" it's in a place where it can be operated.
> AMD-64 is a lot closer to VAX than it is to Itanium.
Don't you need several priviledge rings to run VMS? As far as I know AMD64 only has 2: system and user.
"Everyone is late with 90nm"
http://www.heise.de/newsticker/meldung/46834
Seems to be a reference to this Fishkill article: http://news.com.com/2100-1006-5199327.html
"And of course, the tensions there right now that the global tier one (vendors), outside of Dell (Inc.), who doesn’t really have big SMP systems, those that do have their own proprietary architectures. My view is that AMD64 is as well suited for big SMP machines as it is for scale-out environments, and it’s just a matter of time. But, of course, that’s something we’ll do in concert with our OEM partners."
Sounds like he's talking about Sun here. I mean who else has their own proprietary architecture? IBM perhaps.
An IBM X-Architecture setup would be nice (4-way SMP with X-Architecture interconnects, remote IO etc.).
"SUN as sun have some lush crossbar IP to share with Serverworks in return for exclusive access to the resultant [Opteron] chipsets"
Interesting link through http://www.theinquirer.net/?article=15465
Big volume spike at around 13:50 today. Several million shares. I wonder if it's real and what it means if it is.
> people are moving to opteron linux machines from sparc
> boxen to run large sims
This is great for AMD, but is it great for memory companies? After all, SPARC is already 64 bit and has been for quite a while.
I have to agree with Tench on this one, AMD64 removes a roadblock in front of memory use, but there's not much evidence that it will increase the speed, since 99% of users hadn't hit the block yet anyway. Hmmm, perhaps the dam analogy was better.
Remember, the memory companies were already counting on exponential growth of memory sizes. In order for them to experience unexpected upside there would have to be substantial markets where memory use had been slowed by IA32. Those just aren't there in the quantites needed to make a bump in the huge memory market.
I find that rather unlikely. Since they are due to get model numbers why do they need a brand name at all?
It's an interesting talk. Here are my notes. Some parts are verbatim, others are just notes with minute times if you want to look it up. I think it's obvious what's what.
01:03 There were five of us to design the P6 and one of them is Andy who is
sitting right there
05:30 Intel has one or two design teams that work for the fabs, not the
architects. You can't tell which chips come from them and which
come from Andy and me.
07:50 Number of bugs in a chip is relatively proportional to the number
of transistors (excl. cache)
09:16 Big ideas:
486 pipeline
586 2 pipeline + branch prediction
P6 Out of order
P4 50 little ideas
10:50 Exponential trends are not sustainable
11:10 Usable CPU performance not rising fast enough
12:00 Intel pays attention to hard core gamers
12:17 So lucrative we can't think of anything else
12:44 Asks chipset designers what would it take to put Ethernet on the CPU
gets kicked out of their office for trying to take their jobs
13:55 I personally never worked on Itanium. We did have a lot of interactions
that were pretty exciting, but mostly political not technical
15:00 You have to know that the public is wierd
16:00 My first proposal to Itanium design team was to pick target carefully
16:08 In the beginning the architecture was proposed as a complete replacement
across the board of IA32 - of all Intel chips. Not necessarily
embedded though. But for general purpose computing the belief really
was that by 1997 it would be all Itanium. They were calling it
something else - IA64 - at the time. And so they went off to design
an architecture that would allow that to happen. Now Hewlett-Packard
was involved as well. And at the time workstations weren't dead. And
Hewlett-Packard were making a lot of money from workstations. So
their input to the process was to supply some of the basic ideas as to
how one could match a new architecture to a compiler and really max
up the specmarks. OK, that was kinda <unintelligble> of that day.
And with a heavy emphasis on workstations, because HP liked
workstations, they were selling lots of them. Now the problem was
that workstations meant floating point. Now floating point's not
actually so hard to get. Floating point codes tend to be reasonably
well-behaved and if you can afford the number of pins on the busses
and <unintelligble> units and you don't mess up on the latency of the
functional units you can get there: You can hit whatever performance
numbers you want to hit. The problem is that the workstation market
went away when graphics got good enough on the desktop. You also
notice it used to be you go to a (maybe you don't care, but I noticed)
game arcade, put the quarters in, and some of those games looked
really spectacular, relative to what you could do at home. That's not
true anymore. Nowadays you get your latest nVidia card or whatever
and plug it in, and your graphics are going to be better than what you
see at the arcades. And when that happened, the workstation market
just had no reason to exist, and it kinda just disappeared. So the
emphasis on - the Itanium aspects of the architecture that are related
are now kindof "why is that in there?" And now since that market
kinda went away it became server-only, which was sort of a good thing,
because after all it did have this native large addressing space,
which IA32 did not have, and that's a good market, I mean that's a good
match for the server market. It also is a good match in the sense
that if you are trying to establish a new architecture in terms of its
performance, being in the server market allows you to spend a lot
of money to do that. I mean, you don't have to obey the desktop
economics, and mobile economics. The Itanium process family, first
several chips, maxed out the reticle size. You can not physically
make the chip any bigger. It also maxed out the power. They did
not have a cooling solution that could handle any more, so they
cranked the clock back, till it hit that power, and that's what you
got. In the server space, sure go ahead, do all that, that's not a
problem, but if you're going to compare architectures you have to
somehow subtract out that leeway you gave yourself, and if you want
to do an IA64/32 (which we always did) it becomes really difficult
to do a fair comparison. Now, the other thing that gave me heartburn
and still does to some extent is what instruction set architecture
has ever survived as server-only - 360 comes to mind but that's
because it's mainframe, right, and it's been around so long
[audience] 390, OK lets <inaudible> some of the other ones. Er
lets see, MIPS has had problems sticking in the server space. Alpha,
which I thought was a really good design, but it could not live as a
server chip. There's lots - Sun is going to try do this too, as far
as I can see - it is a lucrative market for computing. But it is a
small market and is a vertical market. And it's not clear how you
are going to make an architecture float there, when there are
architectures below you, that are benefiting from the volumes
of scale that silicon really likes are creeping up for free. They
are coming up your tailpipes without even trying. And if they are
going to do that, you've got no place to go up here. It's not your
CPU that's limiting you up here, it's stuff that they have to pay
for too, like DRAMs and disk drives and things like that. So my issue
is yes, maybe today you are selling chips that are server-only for
several thousand dollars each, what's going to happen in the
future? Can you stay ahead of everyone else? It's not obvious to
me.
And what if you think as I do that the future is actually mobile.
Then you should have designed a new architecture knowing that. If you
don't agree with me, that's fine, actually, but pick your vision and
then chase it. You can't pick everything as your vision - that's a
recipe for mediocrity. If you can't pick your targets you're not
going to hit any of them. So that's my fundamental heartburn about
Itanium is I don't think it had a clear target in the first place
and I think they've veered all over the place in the meantime.
And there were also some new architecture gotchas. I think if we put
all the brainpower in this room and we went off and designed a new
architecture for a few weeks there'd be some really neat ideas in
there. But we need a way to figure out which ones to keep and which
ones to throw out. And if you can't sorta do that you end up with
real trouble. The first proposal I would have is whatever the
architecture we would all go off and design is, lets plan not to sell
it. Lets make a chip out of it and go test the chip and then say
whoops, that didn't work so well throw that feature out, throw that
feature out, this one's a good one, develop it some more. Once we've
done that for a few months, we're going to really know what we want
the second time and we'll be in a lot better position to establish an
architecture in a computing space. If you try to get it right the
first try - I don't know how to do that - I don't think anyone can do
that. You won't be proud of it and noones going to buy it anyway,
right? And they're going to be a little sceptical in the first place
as they should, but getting committed to architecture features that
you thought would work, but you know, you weren't really sure, and you
stuck them in there, but you refused to do the lab thing that I'm
suggesting, and instead you sold it to somebody. Now you have
committed those features for all time on the basis of one guy who
bought 20 of your chips. It makes no sense. I think if you have the
nerve to make a new architecture then go for it. Do it right. Take
the chip to the back room and pound on it. Alpha was reputed to have
done that with their first chip. Pardon? [audience] Yeah. And I
think that's a really good way to look at it - if you're going to
establish an architecture then do it right.
The other thing is, it's really easy to cheat on the benchmarks.
Maybe I shouldn't say cheat - I mean, it's a natural human thing. I'm
not accusing of dishonesty so much as falling prey to human foibles.
You know, you really want this thing to work, so you're going to tend
to show what's good about it, and you're not going to tend to harp so
much on the stuff that doesn't look so hot. So for example, the one
and only Itanium planning meeting I was ever personally at was the
first time that performance projections were presented to Intel's
executives. And the performance projections were put up and I
remember looking at them thinking, those are really amazing. Where
did those come from. I don't see how you get those numbers. I
started asking questions, and it turned out that one man had written
one inner loop, 30 instructions long, tuned the hell out of it and
said that was representative of SPEC. One loop. I said, I don't
understand how you hand coded that, so how would you know that the
compiler can generate that code. If you can show me the compiler
generating that inner loop across most of SPEC benchmarks, then I
retract my objection. And he says, well, of course I haven't done
that, it's too early in the project. I say OK, that's fair enough,
but at least tell the executives what an incredible risk you're asking
them to take by basing everything on 30 instructions that you of all
people on earth can write down and notice how they would work. And of
course that subtlety was lost on the executives. They just said, wow
these are good performance numbers. Can you hit that, Bob? I said
no. Okay. We're good. We're golden. [audience] Their compiler,
theoretical limits, the power - it's really easy to miscompare on
these things. So I really think you have to be careful to evaluate
the features fairly. Things like predication. I'm not a big fan of
predication. We tried some of that at Multiflow, the compilers had a
tough time finding it, and the implementors had a hell of a time
getting it right. It seemed to cost every time we looked at it. You
carried extra semantics around it made linkages between things you
wished weren't there. It's one those things where the compiler... put
it this way, there are people within Intel who are working on Itanium
that still believe that predication is going to win, big. These are
compiler folks, they say, yeah, we suck at it today, but we are
working and we're going to get good at it, and when we do, it
better be in there. And I say, well, OK, when that day comes I am
happy to put the effort in to make my chips do predication. But until
then it's a pain. Can't we like take it out, put it back later when
you're good at it? They said no of course. Things like bus width and
bus speeds. That makes a real difference to any interesting
benchmarks. Maybe not the old SPEC ones but real machines do care
what size the bus is and how fast it runs and the protocol overhead -
getting on and off of it. And the reason that buses aren't infinitely
fast is because it would cost infinte amount of money. We're talking
real money for the pins, real money for the receivers, and the things
you have to do electrically to route the things. P6s if you look at
the dice photo, if I put the dice photo of the P6 back up there, you
can see the bus interface unit on there. It was a lot. Because it
was cache coherent, it had to do snooping there was a lot of
complexity there. All that stuff, you have to be careful. If you are
going to try to compare architectures be really careful to normalise
before you start making claims. I argued this directly with Andt
Grove at one point, because he knew that I had reservations about the
corporate direction with some of Itanium. He said well I can't
reconcile that against the fact that we've shipped some of these
machines, and some of those users love them. And I said, well, if you
want to say, can you make a machine that people love, of course, you
can put anything in there and if it matches their application
perfectly they will love it. I'm trying to say if Intel as a company
is going to base its future on that on that architecture then you have
to do it on an architectural basis. And that has some crude
economics. And right now you're comparing a server-based thing to a
desktop-based thing and it's going to always be like that. And it
doesn't tell you what you need to know. I don't know if I got it
through to him or not, he's a very smart guy, but it's subtle, easy to
get this wrong.
26:45 Another thing was, I was never convinced that a third of the die to
get lousy performance was the right thing. That was the first chip. I
don't know about the second one maybe they got better at it, I just
don't remember. But this is basically what the number was for the
first Itanium and and it just didn't strike me as the right tradeoff.
34:10 Only 3 or 4 people who understood enough of the machine to tackle the
difficult problems. (P4)
35:00 Chaotic scheduling problems
39:20 Public is wierd: FDIV, Serial number
47:55 Visits to Microsoft were routine
50:30 OS company where the last generation and next generation people were
fighting.
50:50 People want secret instructions
51:40 Govt. agencies always want find-leftmost-ones, popcount
56:50 Blue crystals
58:00 Marketing wanted an FPU you could take out.
58:40 Lexus/Toyota
59:10 Wendy's 3-choices marketing example
60:45 Hard to think of non-embarassing things to do to a chip to
differentiate chips. Technologists don't like blue crystals.
Sign of a maturing technology.
62:58 Ride isn't over. Autopilot is.
63:25 Worked on P4, didn't buy a Centrino voluntarily
64:00 Is high clock rate a blue crystal?
Intended to strike a balance between what the public look at while
not getting embarassingly out of synch with what it actually
delivered. "Establish a competitive clock rate, and then fill in
behind it with performance". One of the reasons he left is that
he things Intel needs to go in another direction, not faster
clocks. He didn't want to just do faster clocks.
66:30 Centrino vs. Crusoe.
67:08 64 bit is inevitable because it's so cheap. Clever people say silly
things eg. it's twice as fast. Addressing is easy, just plot the
curve. 36 bits is 1996. You need at least one register to be 64
bits to do addressing, but do you have to switch the entire register
set to be 64 bits. On the other hand making the registers twice as
big doesn't take up much space - does impact clock speed a little.
69:00 Linux vs. Windows
69:50 IO bottleneck
70:21 500 clock cycle latency - what is that all about? Would we do it
different if we started over. More effort in IO.
71:40 IPC/transistor, what could you do with those transistors.
If it has to be compatible then that constrains.
Cache is easy. Doesn't leak. Leakage power is horrible right now.
73:30 You've played the game so many times that you don't see any obvious
wins, so you start looking to the side. They do SMT because there's
nothing really compelling to do on the main stream.
74:30 Donald Norman books. Thinks x86 will die of complexity and Windows
already did. Not entirely wrong on that.
75:50 nVidia is making the chips more programmable and hoping Intel won't
notice. New chips have 64k Icache
76:00 Intel's optical stuff. Speed of light man, I read that on the
Internet. Did you read that? It cracked me up. Pat Gelsinger's
quote. I just loved the quote. The quote said, with this new
optical interconnect, we'll be able to route signals at the speed of
light. What the hell have we been doing all this time? Must be a
misquote.
77:10 A20 bit. Just implement it again and hold my nose.
78:00 Undocumented stuff. Undefined stuff isn't.
79:10 Self-modifying code on 486 has a delay etc. Done in 586. MS flight
simulator used it. They went to the guy and he admitted it didn't
work anyway.
81:00 Reason why an OoO x86 was easier than an OoO 68k was because there
were fewer unaffected condition codes. (or VAX).
81:30 When we first did the P6 none of us, with very few exceptions, had
ever done an x86 before. I had avoided the damn thing because it
was ugly. Cyrix were pretty brave, did all kinds of things and it
still worked, they tested their chips.
82:20 There was no architecture model at all until the P6. They started by
writing a model. A guy who wrote with conserving white space, they
had to lint it to read it, and it became the standard model. He
did the microcoding, very good. Performance model was a
spreadsheet.
So AMD is cherry picking the best Opterons and selling them as the EE model (for blades I presume). Nice though that is I don't think you can compare that with Intel's Banias where all the chips that they yield have that spec.
The fact that the mobile version isn't there is an extra indication that bin splits aren't producing so many of them.
> Athlon 64 is at 2w/12w/30 on 130nm
Where do you get these figures, and what MHz do they refer to
I presume they are deepsleep/halt/fullspeed? They look low to me, esp. the last one.
INTC and AMD both open down 40c.
Is this the low point of the day?
He's a favourite on the Inq letter page. Reader of the Millennium no less:
http://www.theinquirer.net/?article=8691
I imagine it is. The stock market reation to the DELL announcement was pretty lukewarm. AMD rose much more!
When people need "leadership price/performance and 64-bit extension X86 performance", they should be directed to buy Proliant Opterons. But when customers "need to leverage Xeon investment and broad application availability", they are directed to buy Proliant Xeons.
http://www.theinquirer.net/?article=15286
The reasons for going for Xeon sound like complete gobbledegook!