Ramtron - FRAM - ESRAM (RMTR)

[NightOwl]

http://www.intel.com/design/pca/companion/schems/30095301.pdf
http://www.intrinsyc.com/support_mes/intel2700g/carbonado_hw_design_document_1.0.pdf

[Peace Man]

Patience !!!

[NightOwl]

Well Peace...

Looks to me as though it had better start making it's move by the close Wednesday if it plans to do so before the Qtr closes.

[NightOwl]

Thanks for the forecast Peace.

I'm as ready as I'm going to get. Yesterday, today, tomorrow it's all the same to me now. But 8-10 isn't going to get it done. :)

...I am looking for a completely "idiotic" valuation sometime between Q4 of '04 and Q4 of '07.

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[Peace Man]

Get ready. The next run is imminent. The 6-7 week long consolidation should be ending any day now. The next target is 8-10 area.

[NightOwl]

The quick answer is emphatically "No it can't be!"

http://www.siliconinvestor.com/stocktalk/msg.gsp?msgid=19028383

...Or at least that's RMTR's story and they claim they are sticking to it.
http://biz.yahoo.com/bw/030612/125614_1.html

[NightOwl]

Could it be? ...The End of the "beginning?"

http://www.etienglish.com/news/detail_top.html?id=200306120006&art_grad=9

...or does this eTimes just need a better translater?

[NightOwl]

By Ron Wilson
EE Times
(12/06/02 02:52 p.m. EST)
<<The ceremonies then moved into the awards phase, in which fabless companies were recognized for financial performance, novelty or just plain popularity. Xilinx walked away with the award for Most Respected Public Fabless Company, while West Bay Semiconductors took similar honors among private companies.

Genesis Microchip Inc., O2 Micro International Ltd. and Ramtron International Corp. were recognized for outstanding financial performance by a public company, and Atheros Communications Inc., SiberCore Technologies, Silicon Optix Inc. and Wolfson Microelectronics Ltd. were cited for outstanding performance among privately held fabless companies.>>
http://www.siliconstrategies.com/story/OEG20021206S0033

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[timhyma]

As promised-
http://www.investorshub.com/boards/read_msg.asp?message_id=594599

[NightOwl]

Thanks for the invite, but I am pretty much a "one trick pony" kind of bird.<g>

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[timhyma]

Thanks for the response. I plan to work up a profile on it this weekenend. I will post it on the BTS thread.

http://www.investorshub.com/boards/board.asp?board_id=865

Lots of thoughts and ideas there if you want to contribute to the conversation.

Thanks again- Tim

[NightOwl]

Hey! Watch it Peace. <g>

...I have the power of "excommunication" on this thread!<Hoo><Hoo>

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[NightOwl]

Nice signature Tim,

RMTR designs, licenses and sells specialty memories: FRAM(NV); and ESRAM, which is a 1T SRAM replacement technology which competes with pseudo SRAM from a number companies and 1T-SRAM from Mosys.

They aren't saying so publicly but they are hoping that their FRAM IP moves from specialty niche status to main stream at smaller design rules and higher densities. But it must out last contenders like MRAM, OUM and advances in current main stream Flash (NAND) IP.

Its high risk. But hopefully will produce high reward.

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[timhyma]

Could you explain in layman terms what this company does? Seen it mentioned on a prvate board and thought I'd get a "second" opinion <g>


tia- Tim

[Peace Man]

No Inmates - err guests yet. Having fun all by yourself. <g>

[NightOwl]

Embedded DRAM, which could compete on density but is volatile, also has problems of when it comes to cost-effective manufacture, Buss said.

"It's very simple economics. A DSP needs six layers of metal and 26 masks, DRAM needs, say three layers of metal and 26 or 28 masks. The trouble is they are not the same masks and to do the two together you need 32 masks or more. It always comes out unfavorable to embedded manufacture because of the number of layers."

Buss continued: "Ferroelectric memory only requires two additional masks which, given its other characteristics, makes it very attractive." Buss said that in large memory arrays access time was governed by the length and capacitance of the word lines not by underlying materials properties, so he expected access times for FRAM arrasy to come out about the same as their DRAM equivalents.
***
The 1.5-volt chips demonstrate the smallest FRAM cells shown-to-date, measuring only 0.54 square micron, TI claimed. At the 90-nm process node, the generation where TI's first embedded FRAM products are expected to appear, the FRAM cells should be 0.35 square microns, the company said.
http://www.siliconstrategies.com/story/OEG20021107S0003

TI vice president Dennis Buss said that while the company has an embedded-flash capability that it deploys for automotive controllers, embedded flash "made no sense from a cost point of view for the cell phone market vis-à-vis the cost of stacked flash" ? that is, putting bare logic and flash dice in stacked packages.

Both embedded DRAM and embedded flash require an additional six to eight mask layers on top of the 26 or so masks needed for logic. Embedded DRAM also requires burn-in steps that can add about 70 cents per chip, Buss said.

The pseudostatic embedded memories, such as the Mosys Inc. 1T SRAM, can require four to eight additional mask layers, with relatively high power dissipation, he said.
"The real reason that we like FRAM is that it replaces embedded RAM but has zero standby power consumption. If you look at embedded SRAM, the static power can be quite high," said Buss.
http://www.eet.com/semi/news/OEG20021107S0016

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[NightOwl]

http://messages.yahoo.com/bbs?.mm=FN&action=m&board=4687349&tid=rmtr&sid=4687349&...


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[NightOwl]

<<Re: BIG FRAM NEWS
by: xwilyx 10/19/02 12:50 pm
Msg: 20951 of 20955
>>May it make you a rich beyond "my" wildest dreams.<<

I'm not invested in RMTR at the moment?MRAM scares me.

>>Not that I have a clue what "F" means<<

F stands for feature size in a lithography process. Think of square building blocks where each block is the smallest 'dot' you can etch with your lithography beam. The block has a side of length F and therefore has an area of F^2. If you make an FRAM cell that is 4 blocks long and 2 blocks wide, that's 8 blocks, or 8F^2. If each block is .25um on a side, then
F=.25um and
Cell Size = 8F^2 = .5um2

PS, if 1T FRAM is a real possibility, is this good or bad for Ramtron? The materials and structures are different, so what claim does Ramtron have on the IP?

Cova has a primer on their technology and some good general FRAM info:
http://www.covatech.com/technology.htm

Cova and Celis will be presenting in a couple weeks at the 2002 NVMTS:
http://nvm.jpl.nasa.gov/Abstracts02/Kamp=High_Density_FeRAM.pdf
Looks like their roadmap has slipped a bit from the one on the Cova website.>>
http://messages.yahoo.com/bbs?.mm=FN&action=m&board=4687349&tid=rmtr&sid=4687349&...





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[NightOwl]

Well,...

At least Samsung is paying attention:
http://www.siliconstrategies.com/story/OEG20021018S0027
http://www.samsungelectronics.com/semiconductors/product_news/advertise_1034936161796_100.html

Now, if they will just produce it...

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[NightOwl]

Because:
http://www.eetimes.com/story/OEG20020906S0057

There is simply too much at stake.

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[NightOwl]

It would appear that if it isn't "FRAM's Time" now, it soon will be:
http://www.siliconstrategies.com/story/OEG20021007S0053

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[NightOwl]

Ahhhh! You are most kind Admin Matt.

May the labor of your love bear much fruit. <g>

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[Mattu]

Board moved, for you.