Re: If you want to point out a high variation of halt state power consumption, then this hits basically the lowest frequency parts. And for me this hints only that the process is not that mature than the 90 nm which is at the end of its life cycle. Without knowing the distribution in numbers on the different speed grades it is very hard to guess.
Perhaps we are saying the same thing, except you refer to AMD's 65nm process vaguely as being "not mature" relative to their 90nm process, while I am simply trying to point out that process variation and leakage may be the specific attributes that are "not mature" at this point.
Re: Only for the 5000+ we have 90nm and 65 nm standard parts for revision F3/G1. So no other samples can be given. That are also the only matching parts of your list.
What are you trying to prove with just these two samples? Why are they the only ones worth comparing? Sure, they have the same frequency, and the same model number, but they obviously come from different places in AMD's variation curve. In one case, the 65nm 5000+ is the lowest leakage part of all the 65nm parts that AMD currently has in their datasheet, while the 90nm 5000+ is not. The 90nm 5600+ has even lower leakage than the 5000+. So you can't look at a small subset of models to judge the overall variation of the 65nm process. You need a broader sampling.
Re: And again we don't know the differences in the steppings of G1 and F3. The G1 has important differences in grant stop state.
Yes, I know, and I read that document before posting it in my earlier post. I'll admit that we don't know the precise differences between F3 and G1, but I presume that they are minor with respect to the way we compare leakage readings in the C1 states. Nothing in the BIOS writer's guide contradicts that assumption.
Re: And I showed you that comparison between ADA...CZ and ADO...DD is the only which can be valid for a comparison.
Not quite. You *claimed* that ADA/CZ ad ADO/DD were the only valid parts for comparison, but you lacked any convincing reasoning. Like I said above, it just so happens that the ADO5000IAA5DD part is AMD's lowest leakage part in their 65nm lineup, but their ADA5000IAA5CZ part isn't even close to the best in their 90nm lineup.
I am trying to compare lowest leakage device with lowest leakage device, and highest leakage device with highest leakage device in order to show increased process variation. Your choices might stand up from a marketing positioning standpoint, but they have no technical relevance to this topic.
Re: And as you mentioned: "Given that leakage varies strongly with voltage, you can get a sizable savings with just a hundred millivolts or so of reduction." you see difference in voltage of ADO...CZ and ADO...DD parts.
And since I call out these voltage differences and make them part of my analysis, I feel they are well accounted for.
Re: Re: It's a close enough approximation, because dynamic power in C1 state is very low. If it were anything other than insignificant, you would get a visible increase in C1 @ max P-state current draw with higher frequency parts (because dynamic power scales linearly with frequency); but in fact you get lower C1 current draw, because the leakage is lower, because AMD bins them that way due to thermals. >> And this assumption is wrong this should be clear from the Intel numbers I showed. Here you see how clock gating reduces the halt state power draw.
I urge you to look again at the data, which completely supports my thesis above. AMD's C1 min P-state numbers were all taken at 1.1V, across both 90nm and 65nm parts. That made them exactly comparable. And when the max P-state voltage numbers differed, I pointed it out in my analysis. You claim that Intel's numbers disprove this, but I offered to explain that Intel lowered their C1 numbers through voltage reduction techniques. You have yet to disprove this.
Re: I really do not know how you come to a conclusion that there is a problem with process technology (other than yield). The only thing in your arguments that is remaining is that power draw has a variation over the speed bins.
And that one argument was precisely the point. AMD has to downbin all their high leakage 65nm parts as 3600+ parts, which actually are higher leakage than anything they have at 90nm, by far. Now that the 3600+ part has been discontinued, those high leakage parts don't disappear. Unless AMD is throwing them in the trash bin, they instead need to be labeled as 4000+ parts, but now they will be higher leakage than before.
Meanwhile, the more profound conclusion is that small increases in voltage, such as from 1.1V to 1.3V or 1.35V result in a large spike in leakage, such that future quad cores are going to be stuck between a rock and a hard place. At 1.1V, leakage is manageable, but clock frequencies are uncompetitive. At 1.35V, leakage is huge, and power is over budget. It's definitely a smoking gun when trying to answer the question of why AMD has no higher clocking Brisbane part than 2.6GHz, and why Barcelona is being introduced at a meager 2.0GHz frequency. It's the same explanation. At the current voltage, their core frequencies are topped out, but they cannot go to higher voltages, because their power budgets would go up exponentially. Did you not see the claim in this link:
The representative also claimed the major reason for the delays in Barcelona's release has been keeping the voltage of the new CPU at the same level as the current generation of Rev F Opterons. Getting the voltage under control is vital to achieve power consumption that doesn't exceed the current-generation level of 95W, a key feature that AMD has promised for the new range of CPUs.#msg-21526853
Re: variation depends on maturity of process.
At least we agree here. The question is, when does AMD's 65nm process become mature enough to support high frequencies and low leakage. They aren't there yet, and in fact, they are quite a long way from even being where their 90nm process is today.
Re: If I look at these numbers I can only see that the 65 nm parts do significantly better regarding power consumption. They do also better as the 90 nm low power parts. All this is also nothing special because that is clear from a shrink.
I look at the numbers in your analysis, and I note that you are using dynamic workload currents, not currents in C1. This is precisely what you pooh-poohed earlier on. On the other hand, it does show indeed that AMD has improved dynamic power output at 65nm, and now leakage power is a larger ratio of total CPU power. This agrees with my line of thinking.
Moreover, if you look at dynamic power at 1.1V (this is only at 1.0GHz, by the way), you can already see a much larger variation at 65nm, influenced more heavily by leakage. So while this proves your point on active power (something I never disagreed with), it also proves my point on process variation and leakage. Thanks for the data.
Re: Again this shows, that higher frequencies are possible with the 65 nm process than with the 90 nm process from the thermal and power dissipation standpoint.
No, it doesn't. It actually shows that AMD is able to hit 2.8GHz @ 1.325V on 90nm, but they max out at 2.6GHz @ 1.325V on 65nm. It tells me they have gone backwards with frequency potential. Of course, some of this could be design optimization related, but AMD has already had more than half a year to introduce better binning steppings, and so far they haven't. Yet, at the 90nm node, there were steppings galore, so I find it hard to believe that AMD doesn't have the design resources to fix speed path issues over a 6+ month period.
Re: The higher variation in min p-state power consumption only show the capabilities of this process since the higher variation comes from better values.
I would disagree with this. You get better results by reducing variation and having more predictable binning. Otherwise, what does AMD do with all the high leakage parts? They have to sell them as downbins, which are very low frequency, low ASP items without any low power prospects. I'm sure even AMD knows that it's in their best interests to eliminate products coming off the line with these characteristics.
Re: So all you found out is that the AMD 65 nm process is not at the end of it's life cycle but at the beginning and that the 90 nm process is at the end of its life cycle.
Hardly a brilliant conclusion. Yes, this is true, but how long will it take AMD to improve their 65nm process? Intel is ready to introduce 45nm parts next quarter that are actually an improvement over their 65nm mature parts. Are you bold enough to say that AMD's 65nm process "immaturity" is not a problem for them...?
Re: Please also note that AMD delivers already 2.7 GHz versions.
Where are these mythical parts. Not on AMD's price sheet. Not on any vendors in the Froogle engine ( http://www.google.com/products?q=amd+2.7ghz&show=dd ). I've yet to see a part that the Froogle engine can't find. If it's out there, then it's not an officially sanctioned speed grade from AMD. Some vendors have been known in the past to overclock parts and sell them as higher end speed bins.
Re: Agin on why AMD delivers lower speed bins first: This is a yield issue. AMD would be stupid if they would do otherway round. Intel has a different commercial position. They have a lot of fabs and therefore cannot afford to render most production useless. Therefore they start with high speed bins even if the yields are bad then (not a problem because of high price points).
Actually, AMD plays the exact same tricks. One is called the 6000+, which runs at 3.0GHz and has leakage through the roof. Of course, AMD calls this a 125W TDP part, even though it often exceeds the power of a Smithfield Pentium D in many review site system power tests. It's really unsurprising, given that AMD uses 1.4V to bin this part. They have the power to do precisely this to some of their 65nm parts. Why don't they? It's a simple tweak during sort, which is the last step of manufacturing. They can make these parts any time they want. Perhaps, it's because 65nm process variation and leakage at 1.4V would cause thermal problems on production parts. My data supports the notion of a much steeper leakage curve relative to voltage, so this is one possible explanation.
Re: AMD has not the capacity to waste one fab only for high speed bins because then the production is not enough to feed the market.
Maybe you should note what they are doing with Fab30 today. Almost all their 90nm bins are high end, except for a single 3800+ downbin in order to catch the high percentage of parts that do not meet the high end specifications. I think today, AMD uses 4200+ as their 90nm downbin. Either way, they have dedicated Fab30 for this purpose, since Fab36 seems to be unsuitable for creating anything faster than 2.6GHz.
Re: AMD is going the ecominc way and Intel the marketing way.
There is nothing economic about AMD's model. Your theory is completely inconsistent with the profits that Intel continues to make, and the losses that AMD continues to incur. You'll have a hard time convincing anyone that AMD has the right economic solution with their 65nm binning strategy.
Re: That is also the reason why Intel's CPU start usually as rarely available (until yields mature) and AMD can start with full delivery (but low speed grades).
OMG, are you serious...? AMD paper launches every single product that they introduce, and the low speed grade 65nm parts were no exception. They were supposed to launch in December last year, and AMD claimed that they were "shipping" to customers. But they didn't show up from OEMs or from online vendors until late January / early February. People here have wondered how anything can be in transit for almost two months, other than by boat across the Atlantic.
Meanwhile, Intel just introduced their E6x50 parts this past Monday, but they've been available from select retailers a week earlier. Today, only 2 days after launch, they are broadly available. The facts are again in direct conflict with your hypotheses.
Re: Maybe AMD would do it other way if they had enough fabs.
They have 3: Fab30, Fab36, and Chartered. Intel has 3 fabs: D1C, Fab12, and Fab24. They started 65nm on D1D, but this has already transitioned to ramping 45nm. I think AMD has the resources to fix any speed path problems, and any of the marketing or economic positioning problems that you mentioned. The fact that they haven't after 6+ months strongly suggests that there is a more fundamental barrier. You are welcome to your own opinion, but so far you have not introduced anything in conflict with my analysis, so I would propose that my findings stand as yet another possible explanation, at least one that is more intellectually palatable than one in which AMD is trying to cut costs (obviously, not doing a good job), or just can't seem to fix speed path issues (have had more than enough time and resources to do it).
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