POET Technologies Inc (PTK)

[sevenOdouble]

OPL.V Extra + PR Collection + DD Derived from valuable posts:
(last post was 131)


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General Key Valuation Assumptions:
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70904122
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The language used in the government SBIR documents suggest a very high level of confidence in POET:
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70697681
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Dr Taylor. Below are a few IEEE papers on some of the work he was involved in at AT&T Bell Labs:
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70696107
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OPEL Solar, Inc. Supplies GES USA with 4.6 Megawatts of Tracker Systems
OPEL Marks a Milestone with its Largest Tracker Order for the TF-800 Series
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70661011
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NASA's Budget » Procurement ID: NNX11CD96P
Procurement ID NNX11CD96P Overview
http://www.govbudgets.com/fpds_overview/NNX11CD96P/
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POET time lines:
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70528985
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I suspect will be getting a POET update very soon in the new year in the form of a news release. The last NR we received specifically associated to POET was in Sept. I have been thinking more about the photonic memory and Dr Taylor mentioning at the AGM about being the next item for development. That would work into the phase 2 award they were invited to apply for. The first bullet of this years milestones. Q1-2012 Dr. Taylor to produce vertical emitting laser at UConn Lab.
Of course we also have the latest SBIR award to be announced once the ink is dry.
http://www.stockhouse.com/Bullboards/MessageDetail.aspx?p=0&m=30497956&l=0&r=0&s=OPL&t=LIST
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NASA SBIR/STTR Technologies:
insert-text-here
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Defense Market Key Valuation Assumptions:
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70375202
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Summary from Phase 1:
http://investorshub.advfn.com/boards/read_msg.aspx?message_id=70345432
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Here's the Phase II AFRL links which are currently active or recently completed Phase II awards which could evolve into the Phase III applications listed below
Switching Fabrics
http://www.afsbirsttr.com/TopicPreRelease/Profile.aspx?pk=20026
FTA:

Phase III Dual Use Applications:
Military application: Military applications of optical switching fabric include communications satellites, large ships involved in high bandwidth communications and communications ground stations involved in GIG-BE.

Commercial application: Commercial applications for optical switching fabrics include telecommunications industry and avionics.

Monolithic InfraRed pixel structures enabled by Thyristor-HFET EO logic
http://www.afsbirsttr.com/TopicPreRelease/Profile.aspx?pk=20024
FTA:

Phase III Dual Use Applications:
Military application: Military communications satellite programs could benefit from this technology. Commercial application: Commercial satellite programs such as Globalstar and Iridium could also benefit from this technology.

Phased arrays:
http://www.afsbirsttr.com/TopicPreRelease/Profile.aspx?pk=13027
FTA:

Phase III Dual Use Applications:

Successful demonstration of the technology will benefit both military and commercial applications in meeting demand for 10-40 Gb Ethernet transceivers in next generation servers/routers with a III-V digital alternative to Complimentary Metal-Oxide Semiconductor. The technology is ideally suited for application in high speed data transfer via optical crosslinks in satellites.

Ultra Low Power RAM
http://www.afsbirsttr.com/TopicPreRelease/Profile.aspx?pk=20382
FTA:

Phase III Dual Use Applications:
MILITARY APPLICATION: Military applications include communications satellites, avionics and ground terminals.

COMMERCIAL APPLICATION: Commercial applications include commercial satellites, commercial avionics and wireless telecommunications.

This is the new briefing chart for the Phase II work they will undertake:
https://ehb8.gsfc.nasa.gov/sbir/public/documentDownload?severFile=briefchart.pdf&proposalId=SBIR_10_P2_104273&docType=BRIEFCHART
Notice the difference in detail in the top-right image compared with the completed PI briefing chart:
https://ehb8.gsfc.nasa.gov/sbir/public/documentDownload?contractNum=NNX11CD96P&severFile=195944_09_02_2011_10_03_29.pdf&proposalId=SBIR_10_P1_104273
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There are 85 projects, but 79 companies, which means that five companies have received two awards: Cleare Inc, Deployable Space Systems Inc, and three others received 2 awards.

OPEL's management has not yet released the news because the final amounts granted will be negotiated and certainly will be announced when the official amount to be determined. But there will be no big surprise as 63M$ for 85 projects gives us an average of 741K$ each for a max of 750K$.

Interesting info...Only 40% of projects that have completed Phase I were selected for Phase II. ODIS is the first on the list among the four in its class, and ODIS engaged in a readiness level of 4 to finish at 7 which is the highest level for a project without flight tests.
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WASHINGTON -- NASA has selected 85 small business proposals to enter into negotiations for Phase II contract awards through the agency's Small Business Innovation Research (SBIR) Program.
The selected projects have a total value of approximately $63 million. NASA will award the contracts to 79 small high technology firms in 27 states. These competitive awards-based programs encourage U.S. small businesses to engage in federal research, development and commercialization. The programs also enable businesses to explore technological potential, while providing the incentive to profit from new commercial products and services.
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$OPL.V When all of this is brought together for the Q1 nr we should see some more results.

US NavAirwarfare : Integrated Optoelectronics for Optical CDMA
Navy SBIR FY2010.2

Sol No.:
Navy SBIR FY2010.2
Topic No.:
N102-123
Topic Title:
Integrated Optoelectronics for Optical CDMA

Proposal No.:
N102-123-1343
Firm:
ODIS
Three Corporate Drive
Shelton, Connecticut 06484-6222
Contact:
Jianhong Cai
Phone:
[phone]

Abstract:
CDMA is a successful network technology for the wireless industry which relies totally on conventional integrated circuits. The same architecture is equally appealing for telecommunications and is considered an optimum choice for next generation FTTH networks if only low cost implementations were available. The persistent high costs are driven by disparity between optical and electrical components which include WDM capability on the one hand and digital processing on the other. What is required is the ability to merge these onto a single integrated platform so that signals could remain optical at high speeds right to the point that OE conversion was essential. With both capabilities on one die, cost goes down and performance goes up. These same attributes apply to airborne communications. The security enabled is a key aspect and thus multiple recent efforts have focused on the addition of existing PIC devices to a standard CMOS platform. ODIS offers a different solution in the form of POET, a III-V complementary HFET technology on the same integrated circuit as the wavelength division components for OCDMA. This approach achieves the goal and has already solved the main issue of technology compatibility. In this SBIR , POET will be demonstrated for OCDMA.

Benefits:
OCDMA transceivers with 10GB/s and 40 GB/s capability and with a fundamental cost advantage will stimulate a large section of the telecommunications industry. The optoelectronics provides a new technology platform from which to generate smart pixel formats, components for computer buses, AD converters, optical data links and optical memories. The integrated approach is the key to reduced cost and improved reliability.
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Phase 1 Optoelectronic Ultra Low Power RAM was completed on Dec 1 and Opel has been invited to submit for a phase 2 SBIR. In poking around the US Air Force SBIR program website I see that OPEL must submit right away for 2012 funding (typically $750k). Submission window is Dec12 to Jan 11.

http://www.afsbirsttr.com/award/AwardDetails.aspx?pk=17778

PHASE II PROPOSAL SUBMISSIONS

Phase II is the demonstration of the technology that was found feasible in Phase I. Only those Phase I awardees that are invited to submit a Phase II proposal

http://www.acq.osd.mil/osbp/sbir/solicitations/sbir20121/af121.pdf
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MATURING TECHNOLOGY: NASA SELECTS 85 SMALL BUSINESS RESEARCH AND TECHNOLOGY PROJECTS FOR CONTINUED DEVELOPMENT
WASHINGTON -- NASA has selected 85 small business proposals to enter into negotiations for Phase II contract awards through the agency's Small Business Innovation Research (SBIR) Program.
The selected projects have a total value of approximately $63 million. NASA will award the contracts to 79 small high technology firms in 27 states. These competitive awards-based programs encourage U.S. small businesses to engage in federal research, development and commercialization. The programs also enable businesses to explore technological potential, while providing the incentive to profit from new commercial products and services.
$63 million divided up amongst 79 firms would be $797,000 each if divided equally. Might be more (or less) for ODIS.
You would think that this would justify a news release from the company shortly?
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NASA 2010 Small Business Innovation Research (SBIR) Program Phase II awards have been selected and publicly announced on Monday, December 19, 2011 at 3:00 pm. The press release, list of awards, and award abstracts can be downloaded from this page. Please click on any of the items below.
http://sbir.gsfc.nasa.gov/SBIR/sbir2010/phase2/awards/index.html
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Just checked NASA's SBIR website and I think they got the phase II grant
http://sbir.gsfc.nasa.gov/SBIR/sbir2010/phase2/awards/2010firm.html (scroll down)
http://sbir.gsfc.nasa.gov/SBIR/abstracts/10/sbir/phase2/SBIR-10-2-O1.01-9727.html?solicitationId=SBIR_10_P2

For a quick reference here is the phase 1 summary associated with this new phase 2 award.
Phase I Project Summary

Firm: ODIS, Inc
Contract Number: SBIR 2010-I NNX11CD96P
ProjectTitle: OptoelectronicInfrastructure for RF/Optical Phased Arrays

Identification andSignificance of Innovation: (Limit 200 words or 2,000 characterswhichever is less)
The problem addressed is the next generation of device integration for ultra high bandwidth and optoelectronic capability. POET (Planar Optoelectronic Technology) is the innovative solution. It is a monolithic circuit based on epitaxial growth in GaAs. Currently at 1µm wavelength based on quantum wells, it has the potential to operate out to 1.5µm based on quantum dot growth. POET is the only technology to offer high performance complementary electronics monolithically combined with all optoelectronic functions, which includewaveguide based operation of lasers, detectors, modulators, amplifiers, switches and interferometers. It also implements vertical cavity operation of the OE devices simultaneously with the waveguide interconnect. The significance of POET is to displace Si CMOS and thus become the new foundation of the integrated and OE circuit industry. POET addresses many system requirements of future NASA missions. The RF/Optical phased array is the application chosen to define POET capabilities. Operating in Ka band, these arrays launch RF and optical power. POET enables a single chip to define the aperture for both signal types. POET enables RF beam control using optical waveguide signals for beam steering. It also uses vertical cavity arrays on the same chip for directional control of the optical beam.
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Technical Objectivesand Work Plan: (Limit 200 words or 2,000 characters whichever is less)
The overall technical objective was to advance the TRL level of POET such that design issues could be seriously considered. To give more focus, the application of the common aperture for the RF and optical arrays at Ka band was chosen as a challenging prospect to benefit from the integration of optical and electronic devices. The specific objectives pertaining to the common aperture problem are to determine how optical signals could provide power distribution and beam steering for the RF mode of operation and how the POET device functionality could be adapted through innovation to address these requirements. Simultaneously within the same fabrication an objective was to determine how the POET device family could implement and sustain an optical laser beam. The quality and optical flux density of the beam were of great interest since the planar topology may allow coherent operation for the first time by achieving the high brightness associated with supermodes. Another objective was to devise a mechanism to steer the laser beam with electrical signals alone which is only possible with a coherent array achieved with small inter-laser spacing. The work plan consisted of modeling, architecture definition, and POET development through growth and fabrication.
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Technical Accomplishments: (Limit 200 words or 2,000 characters whichever is less)
During the Phase I effort, an implementation of a RF phased array was developed based upon the routing of optical signals in a POET integrated circuit. The RF power is transported as the modulation on an optical carrier and is converted to RF by detection in atraveling wave (TW) photodiode at the antenna. The antenna feed line is designed as the terminating resistance for the detector. To achieve beamsteering by true time delay a new micro-resonator structure is developed that enables field effect control of the waveguide coupling parameter and therefore the differential group delay (DGD). A series feed structure is devised that uses waveguide delay combined with DGD to achieve the correct timing for each transmit cell in both x and y directions. The optical beam is created with a 2DVCSEL array in POET with coupling by anti-guiding to achieve a coherent output. Steering is achieved through control of the local VCSEL drive current. Photomasks were developed to implement the micro-resonator controlled delay, the resonant modulator, the TW detector, the VCSELs and the transistors. Transfer of POET to a DoD manufacturing line continued and transistor speeds (1µm device) of 38.6FGz has been obtained on the first wafers
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NASA Application(s): (Limit100 words or 1,000 characters whichever is less)
NASA applications benefiting from POET integrated circuits are found in all current electronic and optical systems. The RF/optical phased array was addressed here. In addition, POET circuits canbe used to implement photonic ADC and DAC circuits involved in the transmit and receive functions for all radar and imaging systems. Lasercom is another application where POET offers power efficient and high speed transceivers. Internal to the satellite, POET implements all-optical packet switching, OE routing functions and digital processing all with reduced power and higher speed. POET also performs VIS-NIR-SWIR-MWIR-LWIR imaging without the cooling requirement and with integrated readout circuits.
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Non-NASA Commercial Application(s): (Limit 200 words or 2,000 characters whichever is less)
POET is a generalized integrated circuit platform that supports optoelectronics. The commercial market areasidentified are 1) the general wireless market where POET will enable a single chip to combine all of the hand held functions, 2) the microprocessor marketwhich targets the desk top and the blade server functions, and 3) the imaging market including visible and IR which will encompass the camera market forhand-helds. There are many other vertically integrated markets as well such as the laser array market for laser pumps, industrial cutting and medical analysis. A year ago ODIS contracted a market analysis to be performed of the POET value based on existing IP. Based on the IP alone, a value of »$1B was reached considering exclusively the three markets identified. If ODIS were to raiseadditional funds to tackle one of these markets the company value would rise accordingly.

Name and Address ofPrincipal Investigator: (Name, Organization, Street, City, State,Zip)
Geoff W. Taylor
54 Ahern Rd.
Mansfield, CT. , 06269

Name and Address ofOfferor: (Firm,Street, City, State, Zip)
ODIS, Inc.
3 Corporate Drive, Suite 204
Shelton, CT. 06484
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As a distraction from the SP I searched for SBIRs not previously posted. Lee Pierhal has reported several times that OPEL/ODIS has had a history of receiving SBIRs for POET's development. I can't post a link to the search results since nothing in the URL takes you directly to OPEL/ODIS results.
Start here: http://www.dodsbir.net/Awards/Default.asp and type "odis ^OR opel" without the quotes.
Select "firm only" in the bottom drop-down menu and hit search.
The top result is irrelevant but the rest are the correct company.
Also notice that NASA isn't included in the list. I think some of these SBIRs are pre-POET also, but I haven't read them all.
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Links & DD provided in the Air Force SBIR's

The first one listed:

Optoelectronic Ultra Low Power RAM

http://www.afsbirsttr.com/Include/Report/SummaryReport.aspx?pk=B87DCBB3-6910-4774-AE41-3EF24F72D4EC&type=TechMall

Summary of phase 1 (invited to phase 2)

POET also offers the advantage that the SA can deliver data optically from the chip by waveguide or vertically. This means that memory arrays may be coupled vertically. Therefore 3D high density memory is enabled.

I am starting to get the sense that ODIS has a huge amount of work for the number of people they have. Dr Taylor had mentioned at the AGM that they would have something to talk about with RAM in about 3 months. I suspect this got bumped by higher priority work. In the corporate presentation they mention the following.

BAE has world-class GaAsresearch facilities and has numerousPhD researchers working on the continued development of POET

Here is a repost to the Air Force contracts, some excellent detail links are available here. ie The summary’s to the work that has already been done and some of the achievements/advantages that have been realised. Very exiting stuff.

http://www.afsbirsttr.com/TechSearch/Default.aspx?kwa=odis
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A great deal of the enterprise market is skipping (has skipped) 40Gbps, in favour of waiting for 100Gbps.
Even so, in the LAN the best we have right now in 802.ba ... it's really just 10 lanes of 10Gbps in parallel, and device backplanes (like the Cisco CRS3 or ASR9k) are getting stretched thin trying to cope with 100gig (heck the CRS1 was hobbled at 40gig per slot).
WAN- or carrier-side, the OEM roadmaps to watch are those of Alcatel-Lucent, Ciena, Huawei, and a bit unexpectedly, Brocade.
There might also be something worthwhile to look at in e.g. Finisar, since they're closer to the PHY.
But current plans don't really scale well: the expected 400Gbps links are really just 16 lanes of 25Gbps.
Parallelism is fine for bulk traffic, but there's not so much headroom for other traffic (video, etc).
I guess a comparison can be had with the way that serial HDD (SATA) have supplanted IDE (PATA).
Or, think of one Ferrari vs. 16 UPS trucks.
True 100Gbps and beyond should begin once IEEE802.3bj has seen the light of day ... updated drafts planned for next April, with ratification expected by early 2014.
When I look at the timelines in Pellegrino, the 2014-15 period is when things begin to get very rewarding ... and I don't think it's a coincidence.
GLTA,

PS:
Note as to the memory-module market, in some available configurations, the ASR9k has 4TB of RAM. Yes, 4 terabytes of flash memory.
Some techy background reading on the current state of 100Gbps:
http://lacnic.net/documentos/presentaciones/lacnicxiv/100GigabitEthernet-LACNOG.pdf
http://webmedia.company.ja.net/content/documents/shared/networkshop310309/boyle_roadto100gbpsopticalnetworking.pdf
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http://www.afsbirsttr.com/TechSearch/Default.aspx?kwa=odis
Enjoy!
PS click on the interim summaries for current phase I and II grants.
Some of the phase I summaries say "invited for Phase II"
I have been wondering why some of the old Phase ones have never graduated to phase two. I thought either they were unsuccessful or they simply didn't have time to work on them. After reading some of these descriptions I think they will address these "unfinished" projects in due course. In other words we might be hearing about Phase II grants ANYTIME!!!

Here's a nice statement for the switching fabric interim summary:
Anticipated Benefits
"The commercial market opportunity for optical switching fabrics could be significant if the POET optical switch becomes a serious contender for the electronic switching approach. This is expected to happen around 40GB/s data stream rates since the POET cHFET VLSI capability will dramatically outperform CMOS when the feature size gets to 0.1µm. However optical fabrics are only one aspect of one vertical market. There are numerous other vertical markets which POET will dominate and these include the wireless and handheld markets, semiconductor memory market, the server market and the general microprocessor markets to name a few. POET, with OE capability will then become a mainstream technology for all markets for data rates above 40GB/s"
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https://ehb8.gsfc.nasa.gov/sbir/public/technologySearch/searchDetails.do?proposalId=SBIR_10_P1_104273&savedCenter=&savedRecordsPerPage=10&sort=R&savedMatchWord=any&searchText1=searchText&savedSearchText=odis&savedSort=R&taxOrder=Num&recordsPerPage=10&savedPhase=2¢er=&requestFrom=NASASBIRHome&savedTaxOrder=&firmOrder=Alph&program=&matchWord=any&savedFirmOrder=&action=paging&searchText=odis&savedProgram=&savedProgramYear=&programYear=&phase=1

https://ehb8.gsfc.nasa.gov/sbir/docs/public/recent_selections/SBIR_10_P1/SBIR_10_P1_104273/briefchart.pdf
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NASA SBIR 2011 Program Solicitation

It is interesting to note that the ODIS SBIR - Optoelectronic Infrastructure for RF/Optical PhasedArrays is identified as phase 1. However Technical Readiness Level 5 is the exit level.TRL 5 is normally achieved in phase 2 contracts.When I look back at the proposal description it identifies that they started atTRL3 and will end at TRL5.

The program involving ODIS is Subtopic: O1.01 -Antenna Technology

http://sbir.nasa.gov/SBIR/sbirsttr2011/solicitation/SBIR/TOPIC_O1.html
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Phase I Project Summary

Firm: ODIS, Inc
Contract Number: SBIR 2010-I NNX11CD96P
Project Title: Optoelectronic Infrastructure for RF/Optical Phased Arrays

Identification and Significance of Innovation:
The problem addressed is the next generation of device integration for ultra high bandwidth and optoelectronic capability. POET (Planar Optoelectronic Technology) is the innovative solution. It is a monolithic circuit based on epitaxial growth in GaAs. Currently at 1µm wavelength based on quantum wells, it has the potential to operate out to 1.5µm based on quantum dot growth. POET is the only technology to offer high performance complementary electronics monolithically combined with all optoelectronic functions, which include waveguide based operation of lasers, detectors, modulators, amplifiers, switches and interferometers . It also implements vertical cavity operation of the OE devices simultaneously with the waveguide interconnect. The significance of POET is to displace Si CMOS and thus become the new foundation of the integrated and OE circuit industry. POET addresses many system requirements of future NASA missions. The RF/Optical phased array is the application chosen to define POET capabilities. Operating in Ka band, these arrays launch RF and optical power. POET enables a single chip to define the aperture for both signal types. POET enables RF beam control using optical waveguide signals for beam steering. It also uses vertical cavity arrays on the same chip for directional control of the optical beam.

Technical Objectives and Work Plan:
The overall technical objective was to advance the TRL level of POET such that design issues could be seriously considered. To give more focus, the application of the common aperture for the RF and optical arrays at Ka band was chosen as a challenging prospect to benefit from the integration of optical and electronic devices. The specific objectives pertaining to the common aperture problem are to determine how optical signals could provide power distribution and beam steering for the RF mode of operation and how the POET device functionality could be adapted through innovation to address these requirements. Simultaneously within the same fabrication an objective was to determine how the POET device family could implement and sustain an optical laser beam. The quality and optical flux density of the beam were of great interest since the planar topology may allow coherent operation for the first time by achieving the high brightness associated with supermodes. Another objective was to devise a mechanism to steer the laser beam with electrical signals alone which is only possible with a coherent array achieved with small inter-laser spacing. The work plan consisted of modeling, architecture definition, and POET development through growth and fabrication.

Technical Accomplishments:
During the Phase I effort, an implementation of a RF phased array was developed based upon the routing of optical signals in a POET integrated circuit. The RF power is transported as the modulation on an optical carrier and is converted to RF by detection in a traveling wave (TW) photodiode at the antenna. The antenna feed line is designed as the terminating resistance for the detector. To achieve beam steering by true time delay a new micro-resonator structure is developed that enables field effect control of the waveguide coupling parameter and therefore the differential group delay(DGD). A series feed structure is devised that uses waveguide delay combined with DGD to achieve the correct timing for each transmit cell in both x and y directions. The optical beam is created with a 2D VCSEL array in POET with coupling by anti-guiding to achieve a coherent output. Steering is achieved through control of the local VCSEL drive current. Photomasks were developed to implement the micro-resonator controlled delay, the resonant modulator, the TW detector, the VCSELs and the transistors. Transfer of POET to a DoD manufacturing line continued and transistor speeds (1µm device) of 38.6FGz has been obtained on the first wafers

NASA Application(s):
NASA applications benefiting from POET integrated circuits are found in all current electronic and optical systems. The RF/optical phased array was addressed here. In addition, POET circuits can be used to implement photonic ADC and DAC circuits involved in the transmit and receive functions for all radar and imaging systems. Lasercom is another application where POET offers power efficient and high speed transceivers. Internal to the satellite, POET implements all-optical packet switching , OE routing functions and digital processing all with reduced power and higher speed. POET also performs VIS-NIR-SWIR-MWIR-LWIR imaging without the cooling requirement and with integrated readout circuits.

Non-NASA Commercial Application(s):
POET is a generalized integrated circuit platform that supports optoelectronics. The commercial market areas identified are 1) the general wireless market where POET will enable a single chip to combine all of the hand held functions, 2)the microprocessor market which targets the desk top and the blade server functions, and 3)the imaging market including visible and IR which will encompass the camera market for hand-helds. There are many other vertically integrated markets as well such as the laser array market for laser pumps , industrial cutting and medical analysis. A year ago ODIS contracted a market analysis to be performed of the POET value based on existing IP. Based on the IP alone, a value of »$1B was reached considering exclusively the three markets identified. If ODIS were to raise additional funds to tackle one of these markets the company value would rise accordingly.

Name and Address of Principal Investigator: (Name, Organization, Street, City, State, Zip)
Geoff W. Taylor
54 Ahern Rd.
Mansfield, CT. , 06269

Name and Address of Offeror: (Firm, Street, City, State, Zip)
ODIS, Inc.
3 Corporate Drive, Suite 204
Shelton, CT. 0648
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In case anyone was wondering who the second military contractor is that OPEL is working with, it is Boeing Aerospace as per slide 4of the UCONN presentation, at time 13:15 of the video clip. Interestingly Boeing Aerospace is named first then BAE Systems as the two military contractors..

http://mediasite.uchc.edu/Mediasite41/SilverlightPlayer/Default.aspx?peid=da0fe5989c334cbab153a059e257ac44

BAE Systems Inc. (formerly BAE Systems North America) is a major subsidiary of the British defense and aerospace company BAE Systems plc. As per its Special Security Agreement, BAE Systems Inc. operates as a semi-autonomous business unit within BAE Systems controlled at a local level by American management. More at...

http://en.wikipedia.org/wiki/BAE_Systems_Inc.
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This detail did not get the attention it deserved. Producing a vertical emitting laser means the ability to layer POET in the photonic domain. In other words 3d technology in photonics which will far exceed anything that exists in terms of the performanceboost of 3d electronic circuits. Agreed. It might ultimately be that IBM would construct something similar to what's in the article but enhancing it with POET's optical capabilities thus scaling their own technology with the help of ours. Just to lend some support to this idea, I recall that at the AGM we asked about Intel's "Tri-Gate" technology (3D-transistors/FINFET) which was getting some hype at the time. After laughing out loud and correctly calling it "11-year old technology", mangement put our mind further at ease by suggesting that POET could also be used to build chips using FINFET.
I don't know why we would since even the first, rudimentary chips will increase clock speed up to 100GHZ anyway. Why pay Intel a royalty to make it faster? This just highlights the extreme scalability of POET going forward. A few of us also inquired about graphene as a material for ICs and he said the big benefit of POET is compatibility with current technology. So from that I understand that POET can be phased into current technology and then scaled up to gradually eliminate unnecessary/redundant on-chip and chip-to-chip connnections.
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Dr. Taylor to say that the Ultra Low Power Ram was coming along nicely at the AGM. I only have a couple of concerns with that being the result of the current wafer run. One, the SBIR from the Air Force is only a "Phase I" grant where proof-of-concept is all that is expected rather than fully-functioning devices. Secondly, the RAM appears to have optical components also. So if your order of events is correct they may not be able to produce the RAM yet either. Here's the SBIR description for the RAM:
"The digital signal processing and static memory is currently dominated exclusively by CMOS technology with the 6-T cell implementing all static memory. CMOS is the only VLSI technology. However, CMOS is near the end of its scaling potential and it has a severe liability for space applications due to a weakness to radiation. Further, the 6T cell is relatively area and power consumptive and falls well short of the requirements for next generation satellites. ODIS proposes an optoelectronic solution based upon a monolithic technology platform for O and E devices. A key element in the device group is the thyristor which has both laser and detector functions. The thyristor has a very low power storage mode that enables a single device memory cell that may be dynamic or a static memory cell. The dynamic version offers the lowest possible power of any known semiconductor memory. Both the read and write operations are performed optically with on-chip light sources enabling very high speed and high density memory arrays. In addition to the ultra-low power memory , the thyristor also enables a low power logic gate. In this SBIR, ODIS will demonstrate the first integrated low power dynamic ram and logic cell BENEFIT: The digital processor market is several billion dollars with steady growth potential based upon an expending PC industry. As CMOS is constrained by power and speed , the opportunity for GaAs based circuits is significant. The wireless industry is already using all of the GaAs amplifiers that are produced. One can therefore expect a market opportunity for GaAs based memory products with large up-side potential. Digital products can now be added to a growing number of markets addressed by integrated optoelectronics including AD converters, imager products, parallel optical data links, optical interface circuits, phased array receivers and other markets currently dominated by Si."
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Here is a post I made a while ago about the BAE verification process:

There appears to be four steps to the BAE validation work that is ongoing. The first step was to replicate a working electronic transistor device/chip and that was completed in June 2011.

The second step would be to produce wafers of these electronic devices/chips to prove that POET is indeed a commercially viable process and that part will begin at the end of August 2011.

The third step would be to replicate an integrated optical and electronic device/chip. We are still waiting for this announcement.

The fouth step would be to produce wafers of these integrated devices/chips.'

Now, if these wafers that BAE started in August are for an actual product run as suggested tonight rather than a 'test' and due to the fact that no news release has stated otherwise, the wafers will contain chips, as per the second step above, that are purely electrical in nature with no integrated optics. That tweaked my thought process and guess what I came up with - ULTRA LOW POWER RAM as per the Air Force contract.
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From the 2010 Year-End MD&A and Q1 & Q2 MD&As:

During 2011, there are a number of projects planned which will address the short-term and long-term growth plans of the Company including, but not limited to the following:
. . .
Develop a “drop-in” solution for the military marketplace using the POET technology, develop a Military Spec focused device and acquire a Contractor and Government Entity (CAGE) Code for its products.
. . .
Complete the third party validation of the patented POET technology to a fabrication facility that can prove its viability and product potential through OPEL Defense Integrated Systems (“ODIS”).
It would seem to me that since ARFL initiated the BAE work they would expect a functioning product when BAE completes their validation. OPEL has maintained, beginning in Dec. 2010 throughout 2011, that BAE (the "fabrication facility") should be finished during 2011.
Personally I think there's good evidence that the most recent addition to the MD&As (2011Q2). . .
ODIS has contracted with BAE Systems to produce a series of wafers from their foundry with devices developed using the POET technology. The first wafer lot is expected to start in late August
. . . is the final step in the validation. Besides the fact that the clock is ticking to complete the validation "during 2011", both the lasers (optical components) and the transistors (electronic components) have already been demonstrated separately (lasers @UCONN and transistors @BAE) in April and June, respectively:
From 2011Q2 MD&A
In April 2011, OPEL’s ODIS affiliate demonstrated an on chip laser capability for the first time in gallium arsenide. This proves ODIS’s POET technology is capability of producing a monolithic integrated circuit combining both electronic and optical elements
. . .
In June 2011, BAE Systems successfully produced working transistors on gallium arsenide wafers using ODIS, Inc.’s POET technology. ODIS is OPEL’s US affiliate company. This is the first step in validating the ability to commercialize products developed using the POET technology, which is capable of integrating optical and electronic circuits within the same chip
. . .
While it's true that BAE began working on this project before the lasers had been demonstrated, they now have a patent for testing the clock speed of integrated optical busses which references Dr. Taylor's work and presumably was invented to perform the validation of his work:
Here's a link to the patent:
http://www.google.com/patents?id=Z5DNAAAAEBAJ&pg=PA1&dq=optical+bus+inassignee:BAE&hl=en&ei=LTK7TsaiFJPCgAet0pXiCA&sa=X&oi=book_result&ct=result&resnum=1&ved=0CDAQ6AEwAA#v=onepage&q=optical%20bus%20inassignee%3ABAE&f=false

The "Field of Invention" is telling:
This invention relates to the field of test components for photonic communications devices and more particularly to a test for a system to allow the transfer of data between an optical bus and electrical components having different clock speeds.
BAE has the tools to measure the clock speed of integrated circuits with electronic and optical components. Hopefully they are being used as we speak!
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Here's some of the reading I've been doing to understand the grants ODIS has received and the milestones that they are working through. I think I have a much better handle on their probable plan after reviewing this material.
SBIR & Phases Thereof
http://ed.gov/programs/sbir/faq.html
http://www.cpe.vt.edu/gsm/presentations/MikroSBIR_Grants.pdf
TRL
http://en.wikipedia.org/wiki/Technology_readiness_level
http://www.nasa.gov/topics/aeronautics/features/trl_demystified.html
The letter from Mike Pellegrino to Lee Pierhal outlining the key assumptions for their valuation stated:
"It will take between 6 and 18 months for POET to pass through technical readiness level (“TRL”), making POET then desirable for licensing transaction"
http://opelinc.com/news/wp-content/uploads/2011/03/NR-2mar2011ODISValuation.pdf
The clock starts Dec. 31, 2010. This means we could have an announcement as early as tomorrow and as late as next June. The clue from the latest MD&A that some wafers have been commissioned hopefully means they are close to TRL 6-7 where system-specific devices are being prepared and demonstrated.
Now what I'd really like to know is which government body initiated the TRL process for POET which is being tested currently by BAE. This might help us guess who the early adopters are (besides NASA) and what devices are going to be the first to sport POET under the hood.
Exciting times ahead!
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The process of bringing a new technology toward commercialization with SBIR.

The way I now understand the process of bringing a new technology toward commercialization with SBIR support is that there are 3 phases, the third of which is not funded directly through SBIR.

This link . . .
http://www.sbir.gov/sbirsearch/detail/8153
. . . shows Phase 1(2009) & 2(2010) awards to develop optical switching fabrics so that optical signals can come and go without first being converted to an electrical signal for processing. Phase 1 & 2 grants are given for research into possible applications of an idea. When a phase 2 grant is given it means the "proof of concept" has been completed and there is real market applications that can be addressed.

Then there's this . . .
http://opelinc.com/news/wp-content/uploads/2011/08/NR-16Aug2011-ODIS-SPIE.pdf
. . . which is the NR about Dr. Taylor's presence at SPIE. Here's the bit that is related tot he SBIR:

"The second session is ‘Resonant optoelectronic thyristor switches as elements for optical switching fabrics’. Optical switching nodes are described that are suitable for high density optical switching fabrics. The basic element for the optical switch is an optoelectronic thyristor which has three properties considered essential for the switching fabric. First it is binary with on and off states. Second, it is a static storage element. Third, it may be written with optical and electrical inputs. The thyristor is configured as a microdisk and two coupled thyristors constitute a 2x2 switch. Multiple wavelength fabrics may be considered with negligible crosstalk (-20dB) between channels. The routing pattern is written sequentially and optically prior to data transmission."

So what I think has happened is that all of the work done in accordance with the SBIR Phase 1 & 2 grants has lead to the development of using thyristor switches to accomplish what was theorized at the Phase 1 level. Phase 2 has given Dr. Taylor some data to present to the scientific community (SPIE).

Phase 3 would be the commercialization of the technology, and based on fairchij's mention of the TRL I think what we might be seeing with BAE is the approach of stage 6 TRL where real monetization is expected to happen.
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So is the BAE validation already finished? Or "finished enough" to begin seeking contracts?

I've noticed that a few of the NRs have been phrased in the past tense, as though the testing is complete. If so, the wafers they ordered can be considered separate from the validation.
Q2 NR:
"It was announced that BAE Systems also independently validated a working transistor using POET."

Name Change NR:
"BAE Systems independently produced an operational transistor on gallium arsenide wafers, independently validating a critical component of the POET process."

There could be more to test besides working transistors, *but* have a look at these snippets:

GrowthPoint NR
"Based upon the advantages POET presents, a number of U.S. Government Departments and Agencies are developing specific devices using the POET platform, including imaging sensors and ultra-low-power random access memory. . .
" . . .Recently, the POET technology was independently validated by BAE Systems, in their fabrication facility, when working transistors were created using the POET platform."

They use the present-tense to describe the military development of devices (note that no initial license fee has been paid to ODIS as far as we know as of Q2), followed by the past-tense reference to BAE's testing where they claim the whole of the POET tech has been validated by the proof of working transistors.

And finally, the BAE NR:
"BAE Systems entered into a contract with ODIS in 2008, with the intent of replicating specific POET devices in a third-party environment at BAE Systems Reed Microelectronics Center. Over this period, with indirect overview by ODIS staff, BAE Systems engineers methodically tested and confirmed critical electrical elements of POET sub-process steps for the transistors. In the near future, it is intended that these electrical structures will be integrated with the required optical structures."
And
"With an accelerated technical and commercialization roadmap, OPEL is actively addressing future arrangements with device manufacturers, where its platform could be optimized to address device applications based on POET's unique disruptive technology. Today's announcement of a key electronic process validation by BAE Systems brings OPEL a step closer to fully realizing the value of the POET process."

This, in conjunction with fairchij's post seems to send a mixed message. It seems there is at least one more milestone to complete with BAE (OP+EL), *but* they have adopted an "accelerated roadmap" where presumably GrowthPoint will begin to write up the details prior to the fusion of the optics and electronics by BAE.
This begs the question once again: WHAT ARE THOSE BAE WAFERS FOR!?!?

(Courtesy of oogee)
http://www.stockhouse.com/Bullboards/MessageDetail.aspx?p=0&m=30194320&l=0&r=0&s=OPL&t=LIST

oogee's answer to fairchij's comment:
http://www.stockhouse.com/Bullboards/MessageDetail.aspx?p=0&m=30194199&l=0&r=0&s=OPL&t=LIST

The best reference we have remains the Pelegrino Report Schedule A dated February 25, 2011.

Dear Mr. Pierhal:

In accordance with your request, the following are the key assumptions that we used in the construction of our valuation models. It will take between 6 and 18 months for POET to pass through technical readiness level (“TRL”), making POET then desirable for licensing transactions.

MY comment/?… Does BAE validation = Technical readiness?

The nominal remaining economic life for the technology is 22 years. Once deployed, it will take 48 months for penetration of the market to the nominal ending market share.
Product adoption will occur along a Fisher-Pry market adoption curve with a market shape of 0.2000.

ODIS will likely license POET to one or all of the top ten defense contractors.

A time gap that ranges between 2 and 18 months exists that captures when each defense contractor considers executing a license. The defense contractors would pay an initial, nonexclusive license fee that may range between $20 million and $50 million and Defense contractors would make monthly royalty payments thereafter of $250,000 to account for any product-specific royalties.

The first market application for POET in the commercial market would be for generalpurpose microprocessors for server computers
The second market application for POET in the commercial market would be for generalpurpose microprocessors for desktop computers.
The third market application for POET in the commercial market would be for generalpurpose microprocessors for laptop computers.

ODIS will likely license POET to one or all of the top general computer microprocessor manufacturers on an exclusive basis.
ODIS will likely license POET to one or all of the top smartphone microprocessor manufacturers on an exclusive basis.
Smartphone processors would enter the market 48 months from the effective date of the valuation.
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General Key Valuation Assumptions:

The following are key assumptions that are common to all of our valuation models:

• It will take between 6 and 18 months for POET to pass through technical readiness level (“TRL”), making POET then desirable for licensing transactions.

• All revenue models rely on technology licensing fees; thus, there is no cost of goods sold

• ODIS will incur cumulative nominal monthly expenses that current grant revenues satisfy.

• The nominal discount rate for future cash flows is 32.04%

• The base target rate of return used for the discount rate determination is 23.98%.

• The success rate used for the discount rate determination is 25%.

• The holding period used for the discount rate determination would reflect an investment of 22 years (i.e., ODIS is a strategic acquisition, not a financial acquisition).

• The nominal remaining economic life for the technology is 22 years.

• ODIS will incur a 40% nominal income tax rate.

• ODIS will incur a 5% royalty payment to UCONN for the technology licensing.

• ODIS will enjoy an average of 20 remaining years for statutory protection for POET patent portfolio.

• A per-unit royalty would constitute 8.17% of the total value basis for the product.

• Once deployed, it will take 48 months for penetration of the market to the nominal ending market share.

• Product adoption will occur along a Fisher-Pry market adoption curve with a market shape of 0.2000.


Defense Market Key Valuation Assumptions:

The following are key assumptions that we integrated into the valuation model for the defense market:

• ODIS will continue to receive annual revenues from Small Business Innovation Research.

(SBIR) grants and other awards, in accordance with a projected schedule provided by ODIS representatives.

• ODIS will likely license POET to one or all of the top ten defense contractors. SCHEDULE “A”

• Each defense contractor’s licensing decision is an equally probable binary outcome (i.e., they will either license it or not, each occurrence having equal probability).

• Each defense contractor’s licensing decision is independent of other defense contractors (i.e., we modeled no conditional licensing probabilities).

• A time gap that ranges between 2 and 18 months exists that captures when each defense contractor considers executing a license.

• The defense contractors would pay an initial, nonexclusive license fee that may range between $20 million and $50 million.

• Defense contractors would make monthly royalty payments thereafter of $250,000 to account for any product-specific royalties.

Commercial Market Key Valuation Assumptions:

The following are key assumptions that we integrated into the valuation model for the commercial market:

• The first market application for POET in the commercial market would be for generalpurpose microprocessors for server computers.

• The second market application for POET in the commercial market would be for generalpurpose microprocessors for desktop computers.

• The third market application for POET in the commercial market would be for generalpurpose microprocessors for laptop computers.

• ODIS will likely license POET to one or all of the top general computer microprocessor manufacturers on an exclusive basis.

• In each target market, POET platform would nominally allow a manufacturer to capture its current nominal market share deploying it.

Server Market Key Valuation Assumptions:

• Each server would require two processors.
The server processor market would start at 6,939,877 annual units, growing at 0% per year.
Server processors would enter the market 48 months from the effective date of the valuation.
Server processors average $828.89 per unit, which would serve as a basis for a negotiated royalty payment.

Desktop Market Key Valuation Assumptions:

• The desktop processor market would start at 128,200,000 annual units, growing at 1.13% per year.

• Each desktop would require one processor.
Desktop processors would enter the market 48 months from the effective date of the valuation.
Desktop processors average $93.22 per unit, which would serve as a basis for a negotiated royalty payment.

Laptop Market Key Valuation Assumptions:

• The laptop processor market would start at 231,900,000 annual units, growing at 12.43% per year.

• Each laptop would require one processor.
Laptop processors would enter the market 48 months from the effective date of the valuation.
Laptop processors average $93.22 per unit, which would serve as a basis for a negotiated royalty payment.

Smartphone Market Key Valuation Assumptions:

The following are key assumptions that we integrated into the valuation model for the smartphone market:

The Smartphone processor market would start at 188,100,000 annual units, growing at 10.00% in Year 1, 18.18% in Year 2, 15.38% in Year 3, 13.33% in Year 4, 11.28% in Year 5, 9.23% in Year 6, 7.18% in Year 7, 5.13% in Year 8, 3.08% in Year 9, and 1.03% in Year 10.

• The POET platform would nominally allow a smartphone microprocessor manufacturer to capture its current nominal market share deploying it.

• ODIS will likely license POET to one or all of the top smartphone microprocessor manufacturers on an exclusive basis.

• Each smartphone would require one processor.
Smartphone processors would enter the market 48 months from the effective date of the valuation.
Smartphone value creation averages $78.96 per unit, which would serve as a basis for a negotiated royalty payment.
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Patents:
http://www.stockhouse.com/Bullboards/MessageDetail.aspx?s=OPL&t=LIST&m=29618224&l=0&pd=0&r=0
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Interview with Ms. Agudow
http://www.youtube.com/watch?v=EPpY2dL_Mis
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$OPL.V PR Collection:

December 20, 2011 12:14 PM Eastern Time
http://www.cleanenergyauthority.com/solar-energy-news/opel-solar-courting-south-american-market-122011/
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December 19, 2011 12:14 PM Eastern Time
http://eon.businesswire.com/news/eon/20111219006100/en/solar/energy/enphase
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December 05, 2011 12:14 PM Eastern Time
OPEL Solar, Inc. and IG Solar Partner
http://www.marketwire.com/press-release/opel-solar-inc-and-ig-solar-partner-1594513.htm
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http://www.cantechletter.com/2011/11/canadas-10-most-interesting-solar-stocks/
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http://www.laserfocusworld.com/articles/2011/11/gaas-modulator-is-first-poet-alternative-to-si-photonics.html
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NEWS RELEASE October 1st, 2011
Jeffrey “Jay” Johnson appointed as Vice President of North American Sales
http://www.google.be/url?sa=t&rct=j&q=jeffrey%20%E2%80%9Cjay%E2%80%9D%20johnson%20appointed%20as%20vice%20president%20of%20north%20american%20sales&source=web&cd=1&ved=0CCcQFjAA&url=http%3A%2F%2Ffinance.yahoo.com%2Fnews%2FOPEL-Technologies-Inc-ccn-1932629838.html&ei=0VjzTpXKGY6VOsPH8JcB&usg=AFQjCNEUUKjruzYD4RDchT_cs_kUMpInJA&sig2=vRPFHsw6SvB4Z3YMBD51zA
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09/30/12
OPL Delivered the panels & trackers in this article:
http://www.projo.com/business/content/COMMERCE_DIGEST30_09-30-11_R0QLKCB_v10.74dc1.html
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September 19, 2011 09:08 ET
Concentrated Solar Power Market to Grow 45% Through 2016
http://www.marketresearch.com/MarketsandMarkets-v3719/Solar-Power-PV-CSP-Technologies-6510642/
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SHELTON, CONNECTICUT--(Marketwire - April 20, 2011) - OPEL Solar International Inc. ("OPEL" or "the Company") (TSX VENTURE:OPL) announced today that its U.S. affiliate company, OPEL Defense Integrated Systems ("ODIS") has demonstrated laser operation for the first time in a new integrated device as part of its Planar Optoelectronic Technology ("POET") process.
POET creates high-performance devices by fusing light and electronics together on a single chip. Specifically, POET is a semiconductor-manufacturing technology that enables the monolithic fabrication of integrated circuit ("IC") chips containing both electronic and optical elements. By offering components with dramatically lowered cost, together with increased speed, density, and reliability, POET could potentially allow ODIS to fundamentally alter the landscape for a broad range of applications, such as tablet computers and smartphones.
Based on a proprietary Group III-V materials structure, the pulsed vertical cavity surface-emitting laser (VCSEL) operates at 980nm with a 12µm diameter vertical cavity surface and an output power of 1.7mW. In tandem with ODIS' previously-announced integrated detector - a heterostructure field effect transistor (HFET) device - the laser enables inter-circuit optical connections between electronic devices for on-chip applications.
"This has proven, for the first time, an end-to-end technology for on-chip integration of photonic circuits can manipulate light signals on the same semiconductor framework as electronic signals," noted Leon M. Pierhal, CEO of OPEL. "This technology has the potential to overcome the constraints of copper interconnects in silicon-based chips, and it further validates the years of development invested in ODIS, as reflected in the potential market applications for POET technology, as well as its overall importance to our stakeholders."
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SHELTON, CONNECTICUT--(Marketwire - March 2, 2011) - OPEL Solar International Inc. ("OPEL" or "the Company") (TSX VENTURE:OPL) announced today that it is in receipt of a third party valuation of intellectual property developed by its U.S. affiliates OPEL, Inc. and ODIS Inc. The Planar Opto Electronic Technology ("POET"), initially developed by Dr. Geoffrey Taylor at the University of Connecticut and licensed to OPEL, Inc., is a semiconductor fabrication technology that enables the dense packing of digital, analog, and optical circuits on a single gallium arsenide chip. The technology now makes it possible to monolithically integrate a wide number of electronic and optoelectronic functions in a single chip with higher speeds and reduced power consumption compared to Silicon CMOS. For the same functionality, the chip size would be considerably reduced to approximately the size of half a person's thumb nail.
OPEL commissioned a valuation analysis of the POET Technology portfolio ("POET Technology") by an independent, third party valuation firm, Pellegrino & Associates, LLC. The Pellegrino firm performed an analysis of the uses of the POET Technology, the sales it could achieve in its targeted end-markets and likely margins if OPEL can complete its research and development activities successfully and the market adopts the POET Technology. Using a number of valuation techniques and based on technical information provided to it by the Company, the valuation firm has estimated that the POET Technology portfolio could be worth as much as approximately $1 billion. This worth is derived from a range of values; the median value being $966.6 million, while the mean valuation was reported at $1.31 billion.
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SHELTON, CONNECTICUT--(Marketwire - Jan. 19, 2011) - ODIS Inc. announced today that it has received a development contract with the National Aeronautics and Space Administration ("NASA") that will involve a Phase I Award of $100,000. After a period of growing recognition and awards from other United States military branches, NASA has followed the Navy and the Air Force and chosen ODIS's POET platform as a preferred method to develop Optoelectronic infrastructure for RF/Optical phased arrays.
Next generation sensors in space require both optical sensing at 1.5µm and mmw sensing at 35GHz. Normally, separate emitting apertures are required for the optical and RF functions. ODIS will develop the Planar OptoElectronic Technology ("POET") to combine the RF and optical transmit beams for phased array sensors into a single monolithic circuit, with each circuit providing a pixel of the RF array. POET will also enable on-chip electronic control of both RF and optical beam steering angles. With the large number of such spacecraft sensors deployed in extended missions, a huge advantage is gained by the elimination of weight and power along with improvement in reliability.
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OPEL Solar, Ecotech Environmental Technology Launch OPEL Solar Asia

Published on December 22, 2010 at 1:12 AM

OPEL Solar, a USA-based high concentration photovoltaic (HCPV) solar and other solar products manufacturer, declared that it has formed OPEL Solar Asia, in Hong Kong in alliance with Ecotech Environmental Technology, a Hong Kong-based company.

The joint venture will allow the company to enter into the East Asia markets with its HCPV products. The signing of the contract will allow the HCPV technology of the company to penetrate one of the fastest developing solar markets in the world especially the Chinese solar market.

Frank Middleton, OPEL Solar’s COO, said that by signing the joint venture with Ecotech his company has found a well-established associate to penetrate the markets of East Asia and advance its opportunities in China, which is predicted as the most robust solar photovoltaic market in the world. He added that the sound knowledge of Ecotech over the region and its large client-base will put OPEL Solar in an advantageous position with least start-up expenses. Middleton explained that the new venture, OPEL Solar Asia (OSA) has commenced its operations with a 2 MW order for its HCPV system products, which include its solar and tracker modules. He explained that the products, which are meant to meet an order obligation of Ecotech within the People’s Republic of China has opened up a multimillion dollar sales opportunity for the company and resulted in profits in the first year of the joint venture operations.

Leon M. Pierhal, OPEL Solar’s CEO, said that the growing CPV markets in East Asia will allow the company to earn over $100 million as profit in the next four or five years period. He explained that the joint venture decision is taken to sustain the growth of the company in the region.

Source: http://www.opelinc.com/
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2010-10-21 16:28 ET - News Release

Mr. Leon Pierhal reports

OPEL SOLAR, INC., AND THE NATIONAL RESEARCH COUNCIL OF CANADA CELEBRATE THE UNVEILING AND TESTING OF THE SUNRISE SOLAR PROJECT INSTALLATION

Opel Solar Inc. and the National Research Council of Canada, has completed the unveiling and testing of the SUNRISE (Semiconductors Using Nanostructures for Record Increased in Solar cell Efficiency) research project installation at the Institute for Research in Construction's Flexhouse in Ottawa, Ont.

Financed by the Development Bank of Canada (BDC) and the National Sciences and Engineering Research Council of Canada (NSERC), the unveiling and testing of the SUNRISE project represent the culmination of three years of research into utilizing nanostructures to establish a higher level of energy efficiency and output from a concentrated photovoltaic installation. The SUNRISE project is a collaborative research project between Opel, the National Research Council of Canada, the University of Ottawa's Centre for Research and the University of Sherbrooke. The SUNRISE project was focused on developing new, ultra-high-efficient solar cells in combination with high efficiency OPEL Solar concentrator design. When paired with OPEL's state-of-the-art dual-axis tracker, the newly developed panels are very cost-effective and are expected to validate target efficiencies for both cells and the system.

"The company is very excited to see the culmination of three years of research and development by some of the best minds in solar technology with the unveiling of the SUNRISE project," stated Leon Pierhal, president and chief executive officer of OPEL. "This project represents another example of OPEL Solar's industry-leading solar technology development at work."

The SUNRISE project was unveiled and energized this afternoon, at a special ceremony hosted by Gary Goodyear, Minister of State (science and technology) and John McDougall, president of the National Research Council of Canada at the National Research Council of Canada Institute for Research facilities in Ottawa, Ont.
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SHELTON, CONNECTICUT--(Marketwire - Sept. 9, 2010) - ODIS Inc. announced today that it has received a development contract with the Navy Air Warfare Center that will involve a Phase I Award of $150,000. After a period of research conducted by the Navy of ODIS and other competing technologies, the Navy has followed other military branches and chosen ODIS's POET platform as a preferred candidate to develop optical code division multiple access (OCDMA) technology for future avionics systems.
CDMA is widely used in the wireless industry for secure channel allocation to a broad user base. OCDMA has similar potential for the Fiber to the Home (FTTH) application based upon a reduced cost of the optoelectronic interface circuits. ODIS has been awarded a Phase I contract with NAVAIR to develop OCDMA integrated OE circuit approaches for Navy Avionics platforms. The high level of security offered by OCDMA will be deployed at multiple levels in the Department of Defense (DOD) optical avionics multi-core processor networks. The security levels are obtained with the robust encryption techniques afforded by Pseudo-random Noise sequencing in both the time and wavelength domains.
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SHELTON, CONNECTICUT--(Marketwire - April 22, 2010) - Following closely to the previous $750,000 Award in January 2010, ODIS Inc. announced today that it has received two additional AFRL Awards for $850,000, totaling $1.6M so far this year.
The first is a $100,000 Award to develop an "Ultra Low Power RAM", a novel memory cell using the ODIS's optoelectronic thyristor within its III-V Planar OptoElectric Technology ("POET"). Very high density and low storage power may be achieved with the cell represented as the cross-point of an array. The memory design will enable it to be fully compatible with integrated optoelectronic CHFET/thyristor logic and optical I/O. Fabricated in radiation hard gallium arsenide ("GaAs"), the structure enables both static and dynamic operation.
ODIS also announced the receipt of a $750,000 Award to develop "Optoelectronic Directional Couplers for Switching Fabric", switching fabric on a single chip is a device technology that is required to enable the coordination and routing of multiple optical input signals to arbitrary multiple output ports without optoelectronic conversation which is essential technology for optical communication switching hubs and routers. Targeted for future military satellite missions, just like the Phase I, it will greatly reduce power requirements and be designed radiation hard.
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SHELTON, CONNECTICUT--(Marketwire - Jan. 19, 2010) -
ODIS, Inc., announced today that it recently received a $750,000 Award to develop "Monolithic Infra-Red Pixel Structures Enabled by Thyristor-HFET EO Logic". Infra-Red technologies currently require cryogenic cooling to operate and use independent readout integrated circuits. The ODIS technology has been developed to provide the new "state of the art" in integrated approaches to infrared imaging combined with transistor readout circuits.
Dr. Geoff Taylor, Chief Scientist, ODIS, Inc., states that by incorporating these technologies on the same epitaxial structure, the electro-optic operation should enable high sensitivity infra-red imaging in an uncooled environment with significantly improved operating speeds and off-chip communications.
"This breakthrough technology not only has the potential to produce tremendous cost savings for the U.S. Air Force and Space Missile Command," said Leon (Lee) Pierhal, President, ODIS, Inc. "We expect enhanced reliability and higher resolution for current and future satellite missions. In addition, the technology should be able to reduce the cost and improve performance for several commercial markets which become viable with this new capability".