United States Patent 7,936,807
Pan May 3, 2011
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Method and apparatus for reducing the processing rate of a chip-level equalization receiver
Abstract
A method and apparatus for reducing the processing rate when performing chip-level equalization (CLE) in a code division multiple access (CDMA) receiver which includes an equalizer filter. Signals received by at least one antenna of the receiver are sampled at M times the chip rate. Each sample stream is split into M sample data streams at the chip rate. Multipath combining is preferably performed on each split sample data stream. The sample data streams are then combined into one combined sample data stream at the chip rate. The equalizer filter performs equalization on the combined sample stream at the chip rate. Filter coefficients are adjusted by adding a correction term to the filter coefficients utilized by the equalizer filter for a previous iteration.
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Inventors: Pan; Jung-Lin (Smithtown, NY)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 12/535,010
Filed: August 4, 2009
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Related U.S. Patent Documents
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Application Number Filing Date Patent Number Issue Date
11824792 Jul., 2007 7573963
11515169 Aug., 2007 7257152
11210591 Oct., 2006 7116705
60625870 Nov., 2004
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Current U.S. Class: 375/148 ; 375/347
Current International Class: H04B 1/00 (20060101); H04L 1/02 (20060101)
Field of Search: 375/130,140,147,148,150,152,259,260,267,316,346,347 370/310,320,335,328,329,342,441,334
PPP
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