InterDigital Inc (IDCC)

[Gamco]

United States Patent 7,908,545
Hepler , et al. March 15, 2011
Pipeline architecture for maximum a posteriori (MAP) decoders

Abstract
The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

Inventors: Hepler; Edward (Malvern, PA), Starsinic; Michael F. (Philadelphia, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 11/653,014
Filed: January 12, 2007
Related U.S. Patent Documents
Application Number Filing Date Patent Number Issue Date
11219986 Feb., 2007 7181670
10037609 Nov., 2005 6961921
60317855 Sep., 2001
Current U.S. Class: 714/796 ; 375/262; 375/341; 714/794; 714/795
Current International Class: H03M 13/03 (20060101)
Field of Search: 714/794-796 375/262,341

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