United States Patent 7,752,482
Gredone , et al. July 6, 2010
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Hybrid parallel/serial bus interface
Abstract
A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller. Each nibble has at least two start bits whose states collectively represent both a function and/or destination.
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Inventors: Gredone; Joseph (Chalfont, PA), Stufflet; Alfred (Plymouth Meeting, PA), Axness; Timothy A. (Collegeville, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 12/167,938
Filed: July 3, 2008
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Related U.S. Patent Documents
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Application Number Filing Date Patent Number Issue Date
11648938 Jan., 2007 7475273
11151006 Jul., 2007 7240233
11001958 Sep., 2006 7107479
10081466 Dec., 2004 6829718
10080899 Nov., 2004 6823469
10080817 Jan., 2005 6848018
09990060 Jun., 2006 7069464
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Current U.S. Class: 713/600 ; 342/92; 367/65; 367/98; 379/388.03; 379/390.03; 713/320
Current International Class: G06F 5/06 (20060101)
Field of Search: 713/600 367/65,98 379/388.03,390.03 342/92
