United States Patent 7,720,897
Buchert , et al. May 18, 2010
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Optimized discrete fourier transform method and apparatus using prime factor algorithm
Abstract
An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.
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Inventors: Buchert; Ryan Samuel (Phoenixville, PA), Shahrier; Sharif M. (King of Prussia, PA), Becker; Peter Edward (Coatesville, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 11/400,566
Filed: April 7, 2006
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Related U.S. Patent Documents
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Application Number Filing Date Patent Number Issue Date
10782035 Apr., 2006 7028064
10120971 Apr., 2002 6704760
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Current U.S. Class: 708/405
Current International Class: G06F 17/14 (20060101)
