United States Patent 7,636,857
Hepler , et al. December 22, 2009
Data-mover controller with plural registers for supporting ciphering operations
Abstract
A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm "f8" or integrity cipher algorithm "f9".
Inventors: Hepler; Edward L. (Malvern, PA), Gazda; Robert G. (Spring City, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 10/878,729
Filed: June 28, 2004
Related U.S. Patent Documents
Application Number Filing Date Patent Number Issue Date
60573789 May., 2004
Current U.S. Class: 713/189 ; 710/33; 713/181; 726/26
Current International Class: H04N 7/16 (20060101); G06F 13/00 (20060101); G06F 17/30 (20060101)
Field of Search: 713/181,186 726/26 710/33
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