United States Patent 7,539,262
Pan , et al. May 26, 2009
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Method and apparatus for performing chip level equalization using joint processing
Abstract
A method and apparatus for performing chip level equalization (CLE) using joint processing to enhance performance and system throughput using a transmitter having a plurality of transmit antennas and a receiver having a plurality of receive antennas. A channel response matrix is formed between the transmit antennas and the receive antennas to generate a joint channel correlation matrix between the transmit antennas and the receive antennas using a block-FFT (B-FFT) decomposition of the channel response matrix. Estimates of transmitted chip sequences from each of the transmit antennas are generated using minimum mean square error (MMSE) and the joint channel correlation matrix are combined. The combined estimate of the transmitted chip sequences are despread to recover transmitted data.
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Inventors: Pan; Jung-Lin (Selden, NY), DiFazio; Robert A. (Greenlawn, NY)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 11/259,430
Filed: October 26, 2005
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Related U.S. Patent Documents
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Application Number Filing Date Patent Number Issue Date
60636345 Dec., 2004
60642383 Jan., 2005
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Current U.S. Class: 375/267
Current International Class: H04B 7/02 (20060101)
Field of Search: 375/143,144,232-236,260,267,340,350
