Thursday, December 07, 2017 9:51:51 PM
https://www.eetimes.com/document.asp?doc_id=1332696
http://www.zdnet.com/article/iedm-2017-intel-unveils-10nm-technology/
GloFo look like they are got flat on that announcement
some selected nuggets
"The use of cobalt by Intel for contact metallization at 10 nm could emerge as a differentiator in the advanced semiconductor manufacturing battleground. Globalfoundries at 7 nm continues to use the copper/low-k dielectrics"
Also Glofo sticking with Double patterning on the back end, and are making excuses
"Patton told EE Times that sticking with double-patterning for the back end "doesn't mean we aren't dense. It's not just all about pitches. We get to the density target a little bit of a different way."
"The interconnects include 12 metal layers and support multiple voltages for different applications. Intel is using SAQP at the two lowest metal layers (M0 and M1) and SADP (double-patterning) at the next four layers to maximize density. It has also swapped copper for cobalt at the M0 and M1 layers to reduce resistance and improve reliability."
And a real Intel killer they totally low balled the drive current performance improvement on 10nm, probaly to leave the foundries in shock. look at theses numbers
"ntel had previously said that in comparison to 14nm, 10nm would deliver a 25 percent increase in performance or cut power nearly in half. At IEDM, the company said 10nm increases drive current by 71 percent for NMOS transistors and 35 percent for PMOS."
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