Replies to post #33218 on Advanced Micro Devices Inc (AMD)

[sgolds]

Pravin, thank you! Then I was not imagining that power leakage starts to go up non-linearly after pushing the envelope of the process. I do not know this level of chip design, it is the impression I've gotten from reading the experiences of overclockers, and also (on the other side) noting the low power usage of desktop processors used for laptops at lower frequencies. Didn't seem linear to me.

As far a chipguy's response, I've become quite used to an inverse relationship between the politeness of his posts and their accuracy.

:)

[chipguy]

Individual FETs are aware of excessive operating temperature that may be caused by circuit organization and operating frequency. Intel's own specs show that leakage runs away on them at high temp (frequency induced).

Junction temperature depends on power dissipation, package
thermal resistivity, and case temperature. Circuit power to a
very close approximation varies as the square of voltage,
and linearly with load capacitance, operating frequency, and
duty cycle. Your individual FET must be quite brilliant to
discern the operating frequency's specific contribution to its
junction temperature from the other design and operational
variables.

[HailMary]

Individual FETs are aware of excessive operating temperature that may be caused by circuit organization and operating frequency.

Now that is a very good point. High temperatures change the static characteristics of the transistors. Thermal runaway is certainly possible. It really looks to me like Prescott is walking a fine line. I guess it is a good thing they ship with thermal protection to prevent this.