Intel Corp (INTC)

[Hans de Vries]

Notwithstanding slide 34, which I'm aware of:

The 3 channel DDR3 is most likely a (multi-die) package
limitation rather then accurately describing the die layout
on slide 34.

I've seen Nehalem die lay-outs with either one or two rows
of DDR3 I/O cells. which I take to be one or two memory
controllers.

(If the two row version would contain 3 memory controllers
then what is the one row version....)

There's a clear correspondence between the DDR3-DIMM
pin-layout in terms of data-address-control pins and the
I/O cells on the Nehalem die.

This Intel slide combines a 2-channel die with a 2-channel
system diagram:

http://www.cdr.cz/picture/37739/large

Older Intel slides mention 4 DDR3 channels combined with
8-core (2 die?) Nehalems. This might have been before the
actual package was frozen.

http://chip-architect.com/news/Nehalem_off_die_graphics.jpg



Regards, Hans