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$GTCH Typically, an IC’s layout process migration involves

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budfoxfun Member Level  Tuesday, 04/20/21 08:24:12 AM
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$GTCH Typically, an IC’s layout process migration involves vast amount of work due to the impact of process variation on the design geometrical, electrical rules, and reliability at the smaller node. The main aim for layout process migration is typically to attain higher silicon yield, improve the design’s performance, power management, and to achieve major cost reduction. When it comes to porting a microchip from one process to another, typically from a larger to a smaller one, there are many factors that have to go through massive changes, among them are device size/geometrical features, new specifications, process related electrical/physical rules and more.

Delta is seeking to automate this process using deep learning technology for specification-driven IC layout blocks porting. The computer program will be migrating from one process to another ensuring the IC’s layout adheres to all advanced design rules, including deep nanometer support like double patterning. The Delta research will seek to take into consideration the new process electrical and reliability constraints and optimize the data composite rules. Delta is also seeking to perform automatic, multi-dimensional, dynamic layout compaction to minimize the overall chip’s area and increase silicon yield. The data compaction will correct all layout design rules, including complex reliability verification (RV), and DFM (Design for Manufacturing) rules for advanced process.

“Today’s advanced manufacturing technologies present tougher challenges for integrated circuits physical implementation. Microchips are being scaled down to meet the never-ending increasing demand for more functionalities, lower power consumption, higher performance and lower cost, creating major design and manufacturing challenges. Microchips today have to be competitive from density, reliability and variability perspectives. In addition, designs have to obey new manufacturing nodes design rules which creates enormous challenge to meet schedules in a timely manner. Moreover, frequent modifications and updates to advanced nodes design rules make it even more challenging to keep up with manually or automatically. Especially with deep nanometer chips, manufacturing is facing massive challenges in terms of silicon manufacturability, and yield efficiency. Through our research on Delta, we are seeking to introduce an automatic layout migration, compaction and optimization solution to successfully handle all these requirements and updates, with the goal of delivering optimal process migration data that is design rule clean with a click-of-a-button. The never-ending quest to achieve cost effective microchip designs, with more capabilities, and higher performance has become a true challenge, especially as we dive into advanced nanometer nodes of 5nm and below. Delta is aimed to offer a whole world of possibilities with the goal of enabling semiconductor design companies to easily move to the next technology node or an entirely different process, opening new markets horizons and competitive growth,” stated Danny Rittman, the Company’s CTO.


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