Intel Corp (INTC)

[Unkwn]

NO! I insist that it is true..maybe you don't understand what these number actually mean.. few people do.
What I have consistently said is that
there's no basis for competitors to claim they are at 7nm
and Intel is only at 10nm when the transistor densities
are comparable (maybe you actually agree with this..).

Whow, whow whow, what you had written was exactly this:

They'll be bankrupt in a year!!! Can't compete..their (only delivered-in-small-beta-quantities) of 10nm silicon (that's 10nmx10nmx10nm) can't possible compete with the (only-promised-to-deliver) 7nm of the likes of glofo (that's 7nmx14nmx20nm).

That was pure made up bullshit which just showed that you have no clue about how semiconductor processes work. At least you could stop denying it because it really doesn't make you look any better.

Also, you seem to care about the third dimension. Logic processes don't pack transistors in the vertical dimension. There are only layers put onto the transistor layer used for interconnects, but that is a different story. Again, how dense a design can be at the end also depends on how dense those interconnects can be. Maybe you should really start to listen and learn something here, instead of spreading false statements.

So "7nm" is pulled out of a hat...
one dimension of one feature may be 7nm, but the rest of it is much larger. Noone's chip is spherically symmetrical. Noone has a 3-d cubic lattice.

Nobody ever did this on this board, except for you. You were the only one because you obviously had no clue about it. The nm figure used to be the gate length of the transistors in the past, but it isn't anymore. It also wasn't a good metric for actual density at that time either, because it didn't tell much about the actual transistor size or spacing between them, let alone wiring. With current state of the art processes, there is no single metric that describes the potential of a process regarding density. It's a factor of many things, including wiring, layout and tools, as I am repeating myself.

This is true for Intel as well, but they use a well defined and "honest metric" to define density. However, that said, "10nm" is
still an arbitrary normalization figure.

"Now, regarding transistor density: There really is not such a thing."

BS... Who is making things up here? You take the total number of transistors on the device and you ask what is the smallest volume that contains all of them. You then divide the number of transistors by that volume. That defines a transistor density. There is no more fundamental measure than that. And, btw, there's plenty of room to cheat here.

Again, you don't get it and try to pretend to have knowledge that you obviously lack. What would a chip look like that has the maximum number of transistors, what do you think? Since I don't want to wait another day for your answer, I'll give it to you, so sit down and learn something, for christ's sake. The densest structures on chip is not logic, it is memory aka SRAM. You would simply build a memory chip and call it the highest transistor density of the industry. There is just this small issue that it isn't of much use (well, other than simply storing data). That's what I was referring to, when I wrote that there really is no transistor density, because it depends on your design. If you incorporate a lot of low speed memory in your design, you will get a chip with a very high average transistor density, because SRAMs are typically the most dense structures on chip. On the other hand, if you have a look at logic density, which makes more sense, you will still have large variations depending on speed, voltage etc. Take a high performance CPU core, laid out by hand, for instance. That is not tuned for logic density but for highest performance. You can't have a design that is the most dense, highest performance, lowest power - it's physics, you have to make compromises.

By the way: SRAM density also isn't fixed. It depends on power and speed aspects also. If you want fast memory, it won't be as dense as a slow one. Also the lowest power SRAMs aren't normally the densest ones. I guess that's why you have three different kind of SRAM together with their densities named for Intel's 10nm process in the Semiwiki article you posted.

So, please, do me a favor and once and for all and digest this information before you make up new stories.

This density is shape independent. And it defines a length scale.
It would essentially defines the average inter transistor spacing on
a cubic lattice. How big would be this lattice spacing?

If indeed it was a 3-dimensional cubic lattice then we would convert 100 million per cubic mm = 10^8 mm-3 = 10^17 m^-3
(that's per cubic meter). Take the inverse of the cube root of the transistor density, which is 2.15 x 10^-6 m which is 2,150 nanometers. This is 200 times bigger than 10nm!!! It's about the same for all manufacturers. Why is this length scale larger than 10 nm for all manufacturers? WTF does "10nm" mean?

The point is that the shrink that leads to tighter transistor spacing is not 3-dimensional. Instead it is effectively 2-dimensional. There is a (complex) layered substrate of some aggregate thickness ("pitch"), d, and this implies an effective three dimensional density of transistors that is (number/(Area x d)).

The number/Area is roughly the number per gate pitch (and then some; you can use any of the pitches here..there all comparable) squared. Transistor gate pitch, or better MMP (and then some) is about 100nm=10^-7 m. So the area density is about 10^13/m^3. d, the substrate pitches combined, is about 10^-4 mm. So we get 10^13/10^-4 = 10^17 /m^3
which is the 100 Mega/mm^3 that Intel quotes. Intel tells
you what this number is...they could factor out pitch scales and get a much larger number. They don't.
[by the way..these are very rough estimates...I know you'll jump on me for that..but there are limits to everyone's patience and I don't want to waste too much time on this]

Try to sound smart? Here's a famous quote from Friedrich Nietzsche for you:

He who profoundly seeks for knowledge strives for clarity; he who seeks to appear profound to the crowd strives for obscurity.

The third dimension pretty much doesn't matter (yet) for logic processes. If you want the highest logic density per cubic sqmm, just grind your chips down to below 100µm (it is possible - we are doing it for our products to save space). For processors, you basically don't care much about this (other than thermal issues). For mobile, it may matter a bit, e.g. for chip stacked packages.

Actually, if you would like to know who has the highest transistor density per volume, it would be a 3D NAND product, so one of Samsung, Toshiba or Micron. They are at 96 layers now, so you should be able to do the math (at least, you made it seem ...).

Does that help with designing processors? No, at least not yet. It may be the solution to the increasing issues that arise at further process shrinks, but it seems that the tooling is not ready for it yet (memories are much more uniform structures than logic). There's one thing I can assure you: Intel isn't the one who is ahead at this stacking technology. From the foundry players, it is only Samsung which knows how to do it (and they know it very well). Intel just canceled the Micron joint venture, so they are at their own with this now. I don't think of this as a good move by them. I suggested that Intel should outright buy Micron when its share price was in the teens. Would have been a great deal and nice volume fab-filler as well as technology addition (let alone high margin formidable business). Instead, they bought Mobileye - WTF?

So what does 10nm mean?
Really, nothing,

Nobody here said so differently, you just got it wrong. As I have written before, it used to be the gate length, used as a crude measure for density of older processes. This is a completely useless metric now, so they just use it as indication for a roughly 2x shrink. That's why the nodes are typically named at a two thirds the previous node size, since it is about area (I guess you can do the math).

So where 10nm or 14nm or 7nm comes from is
quite arbitrary, quite meaningless. Given how tricky it
is to estimate a metric advantage of X over Y, I simply
don't buy the balderdash of claims by GloFo and TSMC and SS.
And all the analysts are ninnys.

Well, the analysts I have read from typically state this correctly. But again, nobody stated it differently here. Nobody said those numbers had any relation to real structures (fin width matters not at all for density, I hope you get that). Density is just a multidimensional optimization problem (not in the sense of space but design aspects).

As far as the rest of your spew post goes..well you do make some
good points, but mainly you espouse the usual gloom and doom wrt Intel. The sky is falling on Intel, but all others are smoothly sailing along!!! Wow, I have a bridge in my town that I'll sell you for $100.

I never said the sky was falling for Intel. I only said they screwed up a lot, made many poor choices and just didn't execute when they had to. Their costs are increasing significantly and they failed to bring in new business. Now they have AMD with access to similar process tech and this time even a bit earlier, as it seems. That can hurt Intel a lot and AMD is very smart to target the server high end high margin business first. Intel has a lot to lose but, what is even more important for me, AMD has a lot more to win in this. Am I certain about it? No, I am never, I am putting my money according to chances and chances for AMD at the moment are looking quite a lot better than for Intel.

To remain fair: There is more to processes than just density. A lot is also about uniformity, yield and costs in general, power and speed. I think (it's basically impossible to get facts about this) that Intel is not ahead with the cost/yield aspects. They are on par regarding power when you compare with the latest AMD designs but they are definitely still ahead in terms of performance. Only Intel is able to clock its processors up to 4.7 GHz, one of the reasons why AMD is still behind in single thread performance, which still is important. That said, the foundries claim to reach 5 GHz at their 7nm nodes. We'll see what Intel will reach at its "10nm" node and where AMD can get at "7nm". It is clearly an area where Intel historically had much more interest in than the foundries, since most designs made in the foundries are of much lower clock frequencies. There are rumors that the competition between TSMC and Glofo for AMDs increasing chip demand makes them tune their processes more towards higher speed at 7nm. We'll see how that turns out but today, it is still a plus for Intel.

I am down by more than 90% of my original core position in Intel because of these points as of a year ago...unfortunately before the run up from $38 to $55+. No plans to sell more. I considered buying AMD at $16, but regretably didn't...but AMD is a short-term flyer and we will see about how timely their products arrive.

All the previous aside, I think AMD's share price did run up too quick and it is up for a dip while Intel may not be affected that much by the upcoming competition until the mid of next year maybe. Still, it could happen again, actually I find it quite likely, that AMD will be able to obtain the same 30% market share in the mid term, the same it once had more than a decade ago. I guess you can do the math about what this would do with AMDs current share price and will do with Intel's current one.

Can Intel strike back? I bet they will, but first they need a new and decent lead. It takes years in this business to make up for such missteps and time plays agains Intel because they have to keep up with the foundries which are extremely focused on their execution. This may end badly for Intel in the long term but that is by far a certain. I definitely wouldn't short Intel now.