"So you're finally admitting that your "competition only shrinks in one dimension" was made up BS from you and you finally read some actual facts about the latest process generation. That's good, really!"
NO! I insist that it is true..maybe you don't understand what these number actually mean.. few people do.
What I have consistently said is that
there's no basis for competitors to claim they are at 7nm
and Intel is only at 10nm when the transistor densities
are comparable (maybe you actually agree with this..). So "7nm" is pulled out of a hat...
one dimension of one feature may be 7nm, but the rest of it is much larger. Noone's chip is spherically symmetrical. Noone has a 3-d cubic lattice.
This is true for Intel as well, but they use a well defined and "honest metric" to define density. However, that said, "10nm" is
still an arbitrary normalization figure.
"Now, regarding transistor density: There really is not such a thing."
BS... Who is making things up here? You take the total number of transistors on the device and you ask what is the smallest volume that contains all of them. You then divide the number of transistors by that volume. That defines a transistor density. There is no more fundamental measure than that. And, btw, there's plenty of room to cheat here.
This density is shape independent. And it defines a length scale.
It would essentially defines the average inter transistor spacing on
a cubic lattice. How big would be this lattice spacing?
If indeed it was a 3-dimensional cubic lattice then we would convert 100 million per cubic mm = 10^8 mm-3 = 10^17 m^-3
(that's per cubic meter). Take the inverse of the cube root of the transistor density, which is 2.15 x 10^-6 m which is 2,150 nanometers. This is 200 times bigger than 10nm!!! It's about the same for all manufacturers. Why is this length scale larger than 10 nm for all manufacturers? WTF does "10nm" mean?
The point is that the shrink that leads to tighter transistor spacing is not 3-dimensional. Instead it is effectively 2-dimensional. There is a (complex) layered substrate of some aggregate thickness ("pitch"), d, and this implies an effective three dimensional density of transistors that is (number/(Area x d)).
The number/Area is roughly the number per gate pitch (and then some; you can use any of the pitches here..there all comparable) squared. Transistor gate pitch, or better MMP (and then some) is about 100nm=10^-7 m. So the area density is about 10^13/m^3. d, the substrate pitches combined, is about 10^-4 mm. So we get 10^13/10^-4 = 10^17 /m^3
which is the 100 Mega/mm^3 that Intel quotes. Intel tells
you what this number is...they could factor out pitch scales and get a much larger number. They don't.
[by the way..these are very rough estimates...I know you'll jump on me for that..but there are limits to everyone's patience and I don't want to waste too much time on this]
What you should have said is that transistor density doesn't
refer to volume, rather to area divided by aggregate pitches.
Now just look at a table of all the pitches of all features on all the devices of all manufacturers. No pitch for 10nm ever gets close to 10nm. The transistor density is a reliable metric, but it is a two dimensional scaling law. So what does 10nm mean?
Really, nothing,
It's essentially some cherry picked smallest feature size at some
period in time, and marketeers have run amok with it...
for example, the fin width. I think Intel's fin width is smaller than 10nm at 10nm (about 7nm..so Intel should claim they
are at 7nm!) It can be defined as a process wavelength like
EUV.
So where 10nm or 14nm or 7nm comes from is
quite arbitrary, quite meaningless. Given how tricky it
is to estimate a metric advantage of X over Y, I simply
don't buy the balderdash of claims by GloFo and TSMC and SS.
And all the analysts are ninnys.
But a volume shrink involves a simultaneous shrink in 3-d ie, the 2d inter transistor spacing and (all pitches) together. This is what Intel claims to do...it is not what others do. I bet a few shares that TSMC shinks d and not inter-spacing. I'm not sure that pitches are universally unambiguously defined either.
As far as the rest of your spew post goes..well you do make some
good points, but mainly you espouse the usual gloom and doom wrt Intel. The sky is falling on Intel, but all others are smoothly sailing along!!! Wow, I have a bridge in my town that I'll sell you for $100.
I am down by more than 90% of my original core position in Intel because of these points as of a year ago...unfortunately before the run up from $38 to $55+. No plans to sell more. I considered buying AMD at $16, but regretably didn't...but AMD is a short-term flyer and we will see about how timely their products arrive.
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